Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
4-10 Freescale Semiconductor
Execution Timing
• Finish (at the end of the execute stage)—An instruction finishes when the CQ is signaled
that execution results are available to subsequent instructions. Architecture-defined
registers are not updated until the instruction is retired.
• Retire (at the end of the complete stage)—An instruction retires from the CQ after
execution is finished and serializing conditions are met.
• Write back (at the end of the write-back stage)—The results of a retired instruction are
written back to the architecture-defined register.
Figure 4-5 shows the stages of e500 execution units.
Figure 4-5. Execution Stages
4.3 General Timing Considerations
As many as four instructions can be fetched to the IQ during each clock cycle. Two instructions
per clock cycle can be dispatched to the issue queues. Two instructions from the GIQ and one
instruction from the BIQ can issue per clock cycle to the appropriate execution units. Two
instructions can retire and two can write back per cycle.
The e500 executes multiple instructions in parallel, using hardware to handle dependencies. When
an instruction is issued, source data is provided to the appropriate reservation station from either
the architected register (GPR or CRF) or from a rename register.
Complete
Execute
LSU-1 LSU-2 LSU-3 Issue
Fetch2 Decode Execute Complete Issue
Complete Fetch2 Decode Issue
Fetch2 Decode
Fetch1
Fetch1
Fetch1
MU-1 MU-2 MU-3 MU-4
SU1, SU2, and BU Instructions
MU Instructions
Execute
Divide instruction may take 4, 11, 19, 29,
or 35 clock cycles to complete.
Write Back
LSU Instructions
Write Back
Write Back
Complete
Execute
BU-1 BU-2 Issue Fetch2 Decode Fetch1
BU Instructions
Write Back