Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
10-16 Freescale Semiconductor
Auxiliary Processing Units (APUs)
efdmul efdmul
Floating-Point Double-Precision Multiply
efdmul rD,rA,rB
rD
0:63
←
rA
0:63
×
dp
rB
0:63
rA is multiplied by rB and the result is stored in rD. If rA or rB are zero (or a denormalized
number optionally transformed to zero by the implementation), the result is a properly signed zero.
Otherwise, if rA or rB are either NaN or infinity, the result is either pmax (
a
sign
==b
sign
), or nmax
(
a
sign
!=b
sign
). Otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in rD. If
an underflow occurs, +0 or -0 (as appropriate) is stored in rD.
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, SPEFSCR[FINV] is set. If
SPEFSCR[FINVE] is set, an interrupt is taken, and rD is not updated. Otherwise, if an overflow
occurs, SPEFSCR[FOVF] is set, or if an underflow occurs, SPEFSCR[FUNF] is set. If either
underflow or overflow exceptions are enabled and the corresponding bit is set, an interrupt is taken.
If any of these interrupts are taken, rD is not updated.
If the result of this instruction is inexact or if an overflow occurs but overflow exceptions are
disabled, and no other interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point inexact
exception is enabled, an interrupt is taken using the floating-point round interrupt vector. In this
case, rD is updated with the truncated result, the FG and FX bits are properly updated to allow
rounding to be performed in the interrupt handler.
FG and FX are cleared if an overflow, underflow, or invalid operation/input error is signaled,
regardless of enabled exceptions.
0 5 6 10 11 15 16 20 21 31
0 0 0 1 0 0 r D r A r B 0 1 0 1 1 1 0 1 0 0 0