Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Core Complex Overview
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 1-29
1.10 Memory Coherency
The core complex supports four-state memory coherency. Memory coherency is
hardware-supported on the system bus through bus snooping and the retry/copyback bus protocol,
and through broadcasting of cache management instructions. Translation coherency is also
hardware-supported through broadcasting and bus snooping of TLB invalidate transactions. The
four-state MESI protocol supports efficient large-scale real-time data sharing between multiple
caching bus masters.
1.10.1 Atomic Update Memory References
The e500 core supports atomic update memory references for both aligned word forms of data
using the load and reserve and store conditional instruction pair, lwarx and stwcx.. Typically, a
load and reserve instruction establishes a reservation and is paired with a store conditional
instruction to achieve the atomic operation. However, there are restrictions and requirements for
this functionality. The processor revokes reservations during a context switch, so the programmer
must reacquire the reservation after a context switch occurs.
1.10.2 Memory Access Ordering
The core complex supports weakly ordered references to memory. Thus the e500 manages the
order and synchronization of instructions to ensure proper execution when memory is shared
between multiple processes or programs. The cache and data memory control attributes, along
with msync and mbar, provide the required access control; msync and mbar are also broadcast
on the CCB to provide the appropriate control in the case of multiprocessor or shared memory
systems.
1.10.3 Cache Control Instructions
The core complex supports Book E instructions for performing a full range of cache control
functions, including cache locking by line. The core complex supports broadcasting and snooping
of these cache control instructions on the CCB. The e500 core also supports the following
e500-specific cache locking instructions:
• Data Cache Block Lock Clear (dcblc)
• Data Cache Block Touch and Lock Set (dcbtls)
• Data Cache Block Touch for Store and Lock Set (dcbtstls)
• Instruction Cache Block Lock Clear (icblc)
• Instruction Cache Block Touch and Lock Set (icbtls)