Freescale Semiconductor PowerPC e500 Core, Reference Manual

Page: 150 / 548

PowerPC e500 Core Family Reference Manual, Rev. 1
3-20 Freescale Semiconductor
Instruction Model
Figure 3-3 shows how an effective address is generated using register indirect addressing.
Figure 3-3. Register Indirect Addressing for Integer Loads/Stores
The instruction model chapter in the EREF describes effective address calculation. Note that in
some implementations, operations that are not naturally aligned can suffer performance
degradation.
Section 5.7.6, “Alignment Interrupt,” for additional information about load and store
address alignment interrupts.
3.3.1.2.3 Integer Load Instructions
Table 3-11 summarizes the integer load instructions.
Table 3-11. Integer Load Instructions
Name Mnemonic Syntax
Load Byte and Zero lbz r D ,d(r A )
Load Byte and Zero Indexed lbzx r D ,r A ,r B
Load Byte and Zero with Update lbzu r D ,d(r A )
Load Byte and Zero with Update Indexed lbzux r D ,r A ,r B
Load Half Word and Zero lhz r D ,d(r A )
Load Half Word and Zero Indexed lhzx r D ,r A ,r B
Load Half Word and Zero with Update lhzu r D ,d(r A )
Load Half Word and Zero with Update Indexed lhzux r D ,r A ,r B
Load Half Word Algebraic lha r D ,d(r A )
Load Half Word Algebraic Indexed lhax r D ,r A ,r B
Load Half Word Algebraic with Update lhau r D ,d(r A )
Load Half Word Algebraic with Update Indexed lhaux r D ,r A ,r B
Load Word and Zero lwz r D ,d(r A )
No
Store
Load
Yes
0 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Instruction Encoding:
0 5 6 10 11 15 16 20 21 30 31
r A=0?
32 63
GPR ( r A)
0 31
Effective Address
Opcode r D/ r S r A NB Subopcode 0
32 63
GPR ( r D/ r S)
Memory
Interface
Reserved