Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-65
bblels bblels
Branch Buffer Load Entry and Lock Set
bblels
bbea
←
BBEAR
0:29
bbta
←
BBTAR
0:29
bbiab
←
BBEAR
30:31
, BBTAR
30
bbdir
←
BBTAR
31
BranchBufferLoadEntryAndLockSet(bbea, bbta)
An effective address associated with a branch instruction and the corresponding branch target
address are loaded into a BTB entry and locked. It is marked with the prediction that the user
supplies in BBTAR[31]. 1 is taken, 0 is not taken.
If the BTB is disabled, the instruction is a no-op and BUCSR[BBUL] is set. If there already exists
another entry in the BTB associated with the address in the BBEAR and that entry is not locked,
the target address of that entry is overwritten and the entry is then locked. If there already exists a
locked entry in the BTB associated with the address in the BBEAR, the target address of that entry
is overwritten with the target address in the BBTAR and BUCSR[BBLO] is set. If all the ways of
the BTB are locked for the index to which the BBEAR maps, one of the existing entries is
overwritten with the new one and BUCSR[BBLO] is set.
The user can pick the direction of the locked branch target address by programming bit 31 of
BBTAR (BBTAR[BDIR]). If BDIR = 1, the locked address is always predicted as taken; if BDIR
= 0, the locked address is always predicted as not taken.
The bbiab is a 3-bit pointer (BBEAR[IAB0,IAB1]|BBTAR[IAB2]) to the instruction after the
branch. It has values from 0 to 7, based on the location in the cache block of the instruction
following the branch.
This instruction can always be executed in supervisor mode. In user mode, if MSR[UBLE] is
cleared, a privileged instruction exception is taken; if MSR[UBLE] is set, the instruction executes
without a privileged instruction exception.
0 5 6 20 21 31
0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0
BTB APU User