Core Complex Bus (CCB)
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor
13-3
gbl
O
Global. Normally reflected from the M bit of the WIMGE bits; asserted indicates transaction is enabled for
snooping by other masters.
• For burst writes, always negated
• For lock-clear instructions to an L2 cache, always negated
• For address-only transactions that bypass translation, always asserted
ts
O
Transfer start. Asserted by the core to indicate a valid address with attributes.
tt [0:4]
O
Transfer type. Indicates the type of transaction (such as RWITM, WR w/Kill).
wt
O
Write through. Used as a general-purpose information bit for the transaction.
• For
tt[0:4] = READ, 1 indicates instruction-side fetch; 0 indicates data-side read.
• For
tt[0:4] = RWITM/RCLAIM, 1 indicates intent-to-modify at the L1 level.
• For single-beat writes, reflected from the EIMGE bits for that page
• For burst writes, 0 indicates a push for
dcbf
/
dcbst
or for snoop.
• For address-only transactions, always negated
Bus Signals: Snoop Address Bus
sgbl
I
Snoop global. Indicates the transaction is enabled for cache snooping. (Reservation-only snooping also occurs
for non-global write transactions.)
sts
I
Snoop transfer start. Asserted to indicate that the core complex should snoop the transaction this cycle
Bus Signals: Read-1 Data Bus (Read-2 Data Bus is Analogous)
Test and Debug
clkout
O
Clock out mux. Selects the appropriate e500 clock. Refer to
Chapter 8, “Debug Support
.”
ckstp_out
O
Checkstop interrupt. Assertion of this signal by the e500 core is used by system to generate a chip-wide hard
stop and to signal an external CKSTP_OUT.
ude
I
Unconditional debug event interrupt. Asserting
ude sets DBSR[UDE] and, if MSR[DE] is set, causes a debug
interrupt to be taken. Several bits in the debug control registers can be used to override this behavior. See
Section 2.13.1, “Debug Control Registers (DBCR0–DBCR2)
,” for more information.
Provides extra COP functions when enabled by COP control bits.
waitr
I
WAITR select. Assertion results in global
waitr to be selected for the e500 core.
JTAG and TAP
trst
I
JTAG test reset.
Asserted—This input causes asynchronous initialization of the internal JTAG test access port controller. Note
that this signal must be asserted during the assertion of
hreset to properly initialize the JTAG test access port.
tck
I
JTAG test clock. Driven by a free-running clock signal. Input signals to the test access port are sampled on
the rising edge of
tck. TAP output signal changes occur on the falling edge of tck. The test logic allows TCK to
be stopped. asynchronously with respect to all other core complex clocks.
tms
I
JTAG test mode select. Decoded by the internal JTAG TAP controller to determine the primary operation of
the test support circuitry
tdi
I
JTAG test data input. The value present on the rising edge of
tck is loaded into the selected JTAG test
instruction or data register.
Table 13-1. Summary of Selected Internal Signals (continued)
Signal
I/O
Comments, or Meaning when Asserted
Summary of Contents for PowerPC e500 Core
Page 1: ...PowerPC e500 Core Family Reference Manual Supports e500v1 e500v2 E500CORERM Rev 1 4 2005...
Page 36: ...PowerPC e500 Core Family Reference Manual Rev 1 xxxvi Freescale Semiconductor...
Page 38: ...PowerPC e500 Core Family Reference Manual Rev 1 Part I 2 Freescale Semiconductor...
Page 332: ...PowerPC e500 Core Family Reference Manual Rev 1 Part II 2 Freescale Semiconductor...
Page 530: ...Opcode Listings PowerPC e500 Core Family Reference Manual Rev 1 D 50 Freescale Semiconductor...
Page 534: ...PowerPC e500 Core Family Reference Manual Rev 1 E 4 Freescale Semiconductor Revision History...
