Freescale Semiconductor PowerPC e500 Core, Reference Manual

Page: 203 / 548

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-1
Chapter 4
Execution Timing
This chapter describes how the e500 core performs operations defined by instructions and how it
reports the results of instruction execution. It gives detailed descriptions of how the core execution
units work and how these units interact with other parts of the processor, such as the instruction
fetching mechanism, cache register files, and other architected registers. It gives examples of
instruction sequences, showing potential bottlenecks and how to minimize their effects. Finally, it
includes tables that identify the unit that executes each instruction implemented on the core, the
latency for each instruction, and other information useful to assembly language programmers.
References to e500 apply to both e500v1 and e500v2.
For specific timing guidelines and diagrams, refer to the e500 Software Optimization Guide.
4.1 Terminology and Conventions
This section provides an alphabetical glossary of terms used in this chapter. These definitions offer
a review of commonly used terms and point out specific ways these terms are used in this chapter.
NOTE
Some of these definitions differ slightly from those used to describe
previous processors that implement the PowerPC architecture, in
particular with respect to dispatch, issue, finishing, retirement, and
write back, so please read this glossary carefully.
• Branch prediction—The process of guessing the direction and target of a branch. Branch
direction prediction involves guessing whether a branch will be taken. Branch target
prediction involves guessing the target address of a branch. The e500 does not use the
Book E–defined hint bits in the BO operand for static prediction. Clearing BUCSR[BPEN]
disables dynamic branch prediction; in this case the e500 predicts every branch as not taken.
• Branch resolution—The determination of whether a branch prediction is correct. If it is,
instructions following the predicted branch that may have been speculatively executed can
complete (see Completion). If it is incorrect, the processor redirects fetching to the proper
path and marks instructions on the mispredicted path (and any of their results) for purging
when the mispredicted branch completes.
• Complete—An instruction is eligible to complete after it finishes executing and makes its
results available for subsequent instructions. Instructions must complete in order from the
bottom two entries of the completion queue (CQ). The completion unit coordinates how