Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
12-8 Freescale Semiconductor
Memory Management Units
12.3 Translation Lookaside Buffers (TLBs)
The e500 core complex implements six TLB arrays to maximize address translation performance
and to provide ample flexibility for the operating system.
Figure 12-4 contains a more detailed
description of the 2-level MMU structure. Note that for an instruction access, both the I-L1VSP
and the I-L1TLB4K are checked in parallel for a TLB hit. Similarly, for a data access, both the
D-L1VSP and the D-L1TLB4K are checked in parallel for a TLB hit. The instruction L1 MMU
and data L1 MMU operate independently and can be accessed in parallel, so that hits for
instruction accesses and data accesses can occur in the same clock. This figure shows both the
32-bit real addresses used in the e500v1 and the 36-bit real addresses used in the e500v2. It also
shows both the 2-way set associative TLB0 in the e500v1 and the 4-way set associative TLB0 in
the e500v2.
Figure 12-4. Two-Level MMU Structure
Additionally, Figure 12-4 shows that when the L2 MMU is checked for a TLB entry, both TLB1
and TLB0 are checked in parallel. It also identifies the L1 MMUs as invisible to the programming
model (not accessible to the operating system); they are managed completely by the hardware as
inclusive caches of the corresponding L2 MMU TLB entries. Conversely, the L2 MMU is
accessed by the TLB instructions by way of the MAS registers.
A hit to multiple TLB entries in the L1 MMU (even if they are in separate arrays) is considered to
be a programming error. This is also the case if an access results in a hit to multiple TLB entries
in the L2 MMU. If this occurs, the TLB generates an invalid address and TLB entries may be
corrupted (an exception is not reported).
Real Page Number Byte Address
Three 41-bit virtual addresses (VAs)
L1 MMUs
I-L1VSP
I-L1TLB4K
D-L1VSP
D-L1TLB4K
L2 MMUs (unified)
16-Entry Fully-Assoc. VSP Array (TLB1)
256-Entry 2-Way Set Assoc. Array (TLB0)—e500v1
512-Entry 4-Way Set Assoc. Array (TLB0)—e500v2
MAS Registers
Data Access
Instr. Access
‘Invisible’
4–20 (or 24) bits
32 (or 36)-bit Real Address’
12–28 (or 32) bits