Freescale Semiconductor PowerPC e500 Core, Reference Manual

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L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-15
are considered performed at the L1 data cache only if the respective cache contains a valid,
nonshared copy of that address.
11.3.5.2 Sequential Consistency of Memory Accesses
The architecture requires that all memory operations executed by a single processor be
sequentially consistent with respect to that processor as described in the EREF. This means that
memory accesses appear to occur in program order with respect to exceptions and data
dependencies.
The core complex achieves sequential consistency by operating a single data pipeline to the
cache/MMU. Therefore, all memory accesses are presented to the MMU in program order and
exceptions are determined in order. Loads are allowed to bypass stores after exception checking
has been performed for the store, but data dependency checking is handled in the load/store unit
so that a load does not bypass a store with an address match. Newer non-guarded, caching-allowed
loads can bypass older non-guarded, caching-allowed loads. Newer non-guarded.
caching-allowed write-back stores can bypass older non-guarded, caching-allowed write-back
stores if they do not store to overlapping bytes of data.
Note that although memory accesses that miss in the L1 cache are forwarded onto the core
interface unit for future arbitration onto the CCB, all potential synchronous exceptions are
resolved before the cache access. In addition, although subsequent memory accesses can address
the cache, full coherency checking between the cache and the core interface unit is provided to
avoid dependency conflicts.
11.3.5.3 Enforcing Store Ordering with Respect to Loads
The e500 core complex guarantees that any load followed by any store is performed in order (with
respect to each other). The reverse, however, is not guaranteed. An mbar instruction must be
inserted between a store followed by a load to ensure sequential ordering between that store and
that load.
11.3.5.4 Atomic Memory References
The core complex implements lwarx and stwcx. as described in Book E and in Section 3.3.1.7,
“Atomic Update Primitives Using lwarx and stwcx. .” If the EA is not a multiple of 4 for either
instruction, an alignment interrupt is invoked. Executing lwarx or stwcx. to areas marked
write-through causes a DSI exception.
As specified in Book E, the core complex requires that, for stwcx. to succeed, its EA must be to
the same reservation granule as the EA of a preceding lwarx. The core complex makes
reservations on behalf of aligned 32-byte blocks of the memory address space.