Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
1-26 Freescale Semiconductor
Core Complex Overview
1.9.1 Address Translation
The core complex fetch and load/store units generate 32-bit effective addresses. The MMU
translates these addresses to real addresses (32-bit real addresses for the e500v1 core, 36-bit for
the e500v2) (which are used for memory bus accesses) using an interim 41-bit virtual address.
Figure 1-9 shows the translation flow for the e500v1 core.
Figure 1-9. Effective-to-Real Address Translation Flow
Effective Page Number Byte Address
Real Page Number Byte Address
32-bit Effective Address (EA)
32-bit Real Address
4–20 bits* 12–28 bits*
4–20 bits* 12–28 bits*
L2 MMU (unified)
Three 41-bit Virtual Addresses (VAs)
8 bits
MSR
••• IS DS •••
Instruction Access
Data Access
AS
PID0
PID1
PID2
L1 MMUs
Instruction L1 MMU Data L1 MMU
2 TLBs 2 TLBs
* Number of bits depends on page size
(4 Kbytes–256 Mbytes)
16-Entry Fully-Assoc. VSP Array (TLB1)
256-Entry 2-Way Set Assoc. Array (TLB0)