Freescale Semiconductor PowerPC e500 Core, Reference Manual

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L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-3
11.1.1 Block Diagram
The instruction and data caches are integrated with the LSU, the instruction unit, and the core
interface unit in the memory subsystem of the core complex as shown in
Figure 11-1 .
Figure 11-1. Cache/Core Interface Unit Integration
The following sections briefly describe the LSU, the instruction unit, the core interface unit, and
the CCB.
11.1.1.1 Load/Store Unit (LSU)
The data cache supplies data to the general-purpose registers (GPRs) by means of the LSU. The
core complex LSU is directly coupled to the data cache with a 32-byte interface (the width of a
cache block) to allow efficient movement of data to and from the GPRs. The LSU provides all of
the logic required to calculate effective addresses, handles data alignment to and from the data
cache, provides sequencing for load/store multiple operations, and interfaces with the core
interface unit. Write operations to the data cache can be performed on a byte, half-word, word, or
double-word basis.
This section describes the LSU queues that support the L1 data cache. See Section 11.3.5,
“Load/Store Operations ,” for more information on architectural coherency implications of
load/store operations and the LSU on the core complex. Also, see Section 4.4.4, “Load/Store
Execution ,” for more information on other aspects of the LSU and instruction scheduling
considerations.
Instruction
MMU
4
Load Miss
Queue
Data
MMU
Core Complex Bus
L1 Store
Queue
Core Interface Unit
I-Cache
Tags
I-Cache
Status
I-Cache
D-Cache
Tags
D-Cache
Status
D-Cache
8 instructions
(cache block)
DWB
1–4
instructions
forwarded on
cache miss
8-byte
LSU Queues
ILFB
I-Cache
DLFB
instructions
Queues
(LMQ)
Up to a
double
word
forwarded
32-byte
(8 word)
on a
cache
miss
Instruction Unit Load/Store Unit
e500v1
e500v2
e500v1
e500v2