Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Power Management
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 6-3
Table 6-2 describes the core power management states.
6.4 Power Management Control Bits
Although the core can signal power management through the bits shown in Table 6-3 , core power
management is controlled by the integrated device, which may provide additional ways to put the
core into a power-saving state. Interlocks between the core and the integrated device prevent data
loss that could occur if one part of the system powered down before the other had time to prepare.
Table 6-2. Core Power States
State Descriptions
Full on
(default) Default. All internal units are operating at the full clock speed defined at power-up. Dynamic power management
automatically stops clocking individual internal functional units that are idle.
Core
halted Initiated by asserting the halt input. The core complex responds by stopping instruction execution. It then it asserts the
halted output to indicate that it is in the core-halted state. Core complex clocks continue running, and bus snooping
continues to maintain L1 cache coherency. As
Figure 6-1 shows, the core complex is in core-halted state when the
integrated device is in doze state.
Core
stopped Initiated entered when stop is asserted to the core while it is in core-halted state. The core responds by inhibiting clock
distribution to most of its functional units (after the CCB interface idles), and then asserting the stopped output. Internal
PLL clock generation is maintained to allow quick recovery to core-halted or full-on state.
Although snooping cannot occur in core-stopped state, cache coherency can be maintained by allowing the core to
temporarily return to core-halted state, as described below.
Disabling the timer facility and PLL. Additional power reduction is achieved by negating the time base enable ( tben)
input, which suspends timer facility operations. Note that tben controls the time base (and decrementer) in all power
management states. Timer operation is independent of power management except for software considerations required
for processing timer interrupts that occur during core-stopped state. For example, if the timer facility is stopped,
software ordinarily uses an external time reference to update the various timing counters upon restart.
Core power can be further reduced by stopping the internal PLL unit (through the pll_cfg[0:5] inputs) and optionally by
stopping pll_clk. To recover from this complete shutdown, the system must first restart the PLL (through pll_cfg[0:5],
and
pll_clk if it was stopped) and allow time for the PLL to lock before any external interrupt is signaled to the core. This
state is unsuitable for dynamic snooping because of the PLL’s long start-up and lock time. Refer to Table 13-1 for the
encodings of the PLL_CFG[0:5] inputs.
Dynamic bus snooping. To maintain L1 cache coherency, the core complex can be momentarily restored to core-halted
state (by negating
stop; halt remains asserted) to perform snoop operations. After the core complex exits core-stopped
state ( stopped negated), the core complex can recognize snoop transactions on the CCB. While the core is in
core-halted state and
stop and stopped are negated, snoops are issued only to the core complex.
The core returns to core-stopped state when snooping (and any required snoop response and snoop copy-back
transactions on the CCB) completes.
Table 6-3. Core Power Management Control Bits
Bit Description
MSR[WE] Must be set for HID0[DOZE,NAP,SLEEP] to cause assertion of doze, nap, and sleep to system logic.
HID0[DOZE] If MSR[WE] = 1, signals power management logic to initiate device-level doze state. The core complex enters
core-halted state after integrated device logic asserts halt.
HID0[NAP] If MSR[WE] = 1, signals power management logic to initiate device nap mode. The core complex enters
core-stopped state (with its time base enabled) after integrated device logic asserts
stop.