Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
12-16 Freescale Semiconductor
Memory Management Units
Note that when an L2 TLB entry is invalidated by executing a tlbwe instruction that clears a valid
bit, any corresponding entry in the L1 TLB arrays is also automatically invalidated. In addition,
when L2 TLB entries are invalidated by the execution of tlbivax, by the detection of a TLB
invalidate command broadcast by another processor, or by a flash invalidate operation,
corresponding L1 TLB entries are also invalidated as described in Section 12.4.4, “TLB Invalidate
(tlbivax) Instruction.”
12.3.4 L1 and L2 TLB Access Times
The L1 TLB arrays are checked for a translation hit in parallel with the on-chip L1 cache lookups
and incur no penalty on an L1 TLB hit. If the L1 TLB arrays miss, the access proceeds to the L2
TLB arrays. For L1 instruction address translation misses, the L2 TLB latency is at least 5 clocks;
for L1 data address translation misses, the L2 TLB latency is at least 6 clocks. These access times
may be longer depending on some arbitration performed by the L2 arrays for simultaneous
instruction L1 TLB misses, data L1 TLB misses, the execution of TLB instructions, and TLB
snoop operations (snooping of TLBINV operations on the CCB).
Note that when a TLBINV operation is detected on the CCB, the L2 MMU arrays become
inaccessible due to the snooping activity caused by the TLBINV.
12.3.5 The G Bit (of WIMGE)
The G bit provides protection from bus accesses due to speculative and faultable instruction
execution. A speculative access is defined as an access caused by an instruction that is downstream
from an unresolved branch. A faultable access is defined as an access that could be cancelled due
to an exception on an uncompleted instruction.
On the e500, if the page for this type of access is marked with G = 0 (unguarded), this type of
access may be issued to the CCB regardless of the completion status of other instructions. If G = 1
(guarded), the access stalls (if it misses in the cache) until the exception status of any instructions
in progress is known.
When G = 1 for the page, data accesses that miss in the cache are not issued to the CCB until the
instruction is known to be required by the program execution model; that is, all previous
instructions will have completed without exception and no asynchronous interrupts occur between
the time that the access is issued to the CCB and the time that the CCB transaction request
completes. For reads, this requires that the data be returned and the instruction is retired. For
writes, the instruction retires when the write transaction is committed to be sent to the CCB.
Note that after an access with G = 1 is begun to the CCB, it is guaranteed to be completed. That
is, after the address tenure is acknowledged on the CCB, the core completes the access, even if an
asynchronous interrupt is pending.