Freescale Semiconductor PowerPC e500 Core, Reference Manual

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L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-7
There are status bits associated with each cache block, used to implement the
modified/exclusive/shared/invalid (MESI) cache coherency protocol. The coherency protocols are
described in
Section 11.3, “Cache Coherency Support .”
11.2.2 L1 Instruction Cache Organization
The L1 instruction cache is organized as shown in Figure 11-3 .
Figure 11-3. L1 Instruction Cache Organization
Each block consists of eight instructions, 1 status bit, 1 lock bit, and an address tag. Also, although
it is not shown in
Figure 11-3 , the instruction cache has 1 parity bit/byte, yielding 32 parity bits for
each line.
As with the data cache, each instruction cache block is loaded from an 8-word boundary (that is,
bits 27–31 of the physical addresses are zero). Instruction cache blocks are also aligned on page
boundaries. Also, PA[20:26] provides the index to select a set, and PA[27:28] selects an instruction
within a block. The tags consist of physical address bits PA[0:19]. Address translation occurs in
parallel with set selection (from PA[20:26]).
The instruction cache can be accessed internally while a fill for a miss is pending (allowing hits
under misses). Although the data cannot be used, the hit information stops a subsequent miss from
requesting a fill. In addition, subsequent misses can also be sent to the memory subsystem before
the original miss is serviced (allowing misses under misses). When a miss is actually updating the
cache, subsequent accesses are blocked for 1 cycle. (But up to four instructions being loaded into
the instruction cache can be forwarded to the instruction unit simultaneously.)
128 Sets
Way 5
Way 6
Way 7
Way 4 Address Tag 4
Address Tag 5
Address Tag 6
Address Tag 7
Way 1
Way 2
Way 3
Way 0 Address Tag 0
Address Tag 1
Address Tag 2
Address Tag 3
Status
Status
Status
Instructions [0–7]
Status
Instructions [0–7]
Instructions [0–7]
Instructions [0–7]
Status
Status
Status
Instructions [0–7]
Status
Instructions [0–7]
Instructions [0–7]
Instructions [0–7]
8 Instructions/Block