Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
11-6 Freescale Semiconductor
L1 Caches
11.2 L1 Cache Organization
The L1 instruction and data caches of the core complex are both organized as 128 sets of eight
blocks with 32 bytes in each cache line. The following subsections describe the differences in the
organization of the instruction and data caches.
11.2.1 L1 Data Cache Organization
The L1 data cache is organized as shown in Figure 11-2 .
Figure 11-2. L1 Data Cache Organization
Each block consists of 32 bytes of data, 3 status bits, 1 lock bit, and an address tag. For the L1 data
cache, a cache block is the 32-byte cache line. Also, although it is not shown in
Figure 11-2 , the
data cache has 1 parity bit/byte (4 parity bits/word).
Each cache block contains 8 contiguous words from memory that are loaded from an 8-word
boundary (that is, physical addresses bits 27–31 are zero). Cache blocks are also aligned on page
boundaries. Physical address bits PA[20:26] provide the index to select a cache set. The tags
consist of physical address bits PA[0:19]. Address translation occurs in parallel with set selection
(from PA[20:26]). Lower address bits PA[27:31] locate a byte within the selected block.
The data cache can be accessed internally while a fill for a miss is pending (allowing hits under
misses) and the data from a hit can be used as soon as it is available. The LSU forwards the critical
word to any pending load misses and allows them to finish. Later, when all the data for the miss
has arrived, the entire cache line is reloaded. In addition, subsequent misses can also be sent to the
memory subsystem before the original miss is serviced (allowing misses under misses). Up to four
misses can be pending in the load miss queue. See
Section 4.4.2.1, “Load/Store Unit Queueing
Structures ,” for more information.
128 Sets
Way 5
Way 6
Way 7
Way 4 Address Tag 4
Address Tag 5
Address Tag 6
Address Tag 7
Way 1
Way 2
Way 3
Way 0 Address Tag 0
Address Tag 1
Address Tag 2
Address Tag 3
Status
Status
Status
Words [0–7]
Status
Words [0–7]
Words [0–7]
Words [0–7]
Status
Status
Status
Words [0–7]
Status
Words [0–7]
Words [0–7]
Words [0–7]
8 Words/Block