Freescale Semiconductor PowerPC e500 Core, Reference Manual

Page: 219 / 548

Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-17
• For a caching-inhibited stwcx. instructions, the address tenure must complete on the CCB.
If a bus error occurs, the stwcx. completes and clears CR0[EQ], indicating that the stwcx.
did not succeed.
Guarded lmw and stmw instructions can be interrupted before the instruction completes and
restarted after the interrupt is serviced.
4.3.5 Memory Synchronization Timing Considerations
This section describes the behavior of the msync and mbar instructions as they are implemented
by the e500.
4.3.5.1 msync Instruction Timing Considerations
The msync instruction provides a memory barrier throughout the memory hierarchy. It may be
used, for example, to ensure that a control bit has finally been written to its destination control
register in the system before the next instruction begins execution (such as to clear a pending
interrupt). By its nature, it also provides an ordering boundary for pre- and post-msync storage
transactions.
On the e500, msync waits for preceding data memory accesses to reach the point of coherency
(that is, visible to the entire memory hierarchy), then it is broadcast on the e500 bus. An msync
does not finish execution until all storage transactions caused by prior instructions complete
entirely in its caches and externally on the bus (address and data complete on the bus, excluding
instruction fetches). No subsequent instructions and associated storage transactions are initiated
until such completion.
It completes only after its successful address bus tenure (without being ARTRYed). Execution of
msync also generates a SYNC command on the bus (if HID1[ABE] is set), which also must
complete normally (without address retry) for the msync instruction to complete. Subsequent
instructions can execute out of order, but they can complete only after msync completes.
It is the responsibility of the system to guarantee the intention of the SYNC command on the
bus—usually by ensuring that any bus transactions received before the SYNC command from the
core complex complete in its queues or at their destinations before completing the SYNC
command on the CCB.
4.3.5.2 mbar Instruction Timing Considerations
The mbar instruction provides an ordering boundary for storage operations. Its architectural intent
is to guarantee that storage operations resulting from previous instructions occur before any
subsequent storage operations occur, thereby ensuring an order between pre- and post-mbar
memory operations. It may be used, for example, to ensure that reads and writes to an I/O device
or between I/O devices occur in program order or to ensure that memory updates occur before a
semaphore is released.