PowerPC e500 Core Family Reference Manual, Rev. 1
12-18
Freescale Semiconductor
Memory Management Units
The implementation of the tlbre, tlbwe, tlbsx, tlbivax, and tlbsync instructions is summarized in
this section. The extended (64-bit) forms of these instructions are invalid for the core complex. See
Section 3.1.4, “Unsupported Book E Instructions
.” Although the tlbre, tlbwe, tlbsx, tlbivax, and
tlbsync instructions are defined by Book E, their specific functions are defined by Freescale
Book E.
12.4.1 TLB Read Entry (tlbre) Instruction
The tlbre instruction causes the contents of a single TLB entry to be extracted from the L2 MMU
and placed in the corresponding fields of the MMU assist (MAS) registers. The entry extracted is
specified by the TLBSEL, ESEL, and EPN fields of the MAS0, and MAS2 registers. The contents
extracted from the L2 MMU are placed in MAS1, MAS2, and MAS3. Note that for the e500v2, if
HID0[EN_MAS7_UPDATE] = 1, MAS7 is also updated with the four highest-order bits of
physical address for the TLB entry. See
Section 12.7.2, “MAS Register Updates
,” for details on
which MAS register fields are updated.
The following RTL describes the e500 core complex tlbre implementation:
tlb_entry_id = MAS0(TLBSEL, ESEL) || MAS2(EPN)
result = L2MMU(tlb_entry_id)
MAS0, MAS1, MAS2, MAS3, (and MAS7 if HID0[EN_MAS7_UPDATE] = 1) = result
Note that architecturally, if the instruction specifies a TLB entry that is not found, the results
placed in MAS0–MAS3 (and optionally, MAS7) are undefined. However, for the e500, the
TLBSEL, ESEL and EPN fields always index to an existing L2 TLB entry and that indexed entry
is read. Note that EPN bits are only used to index into TLB0. In the case of TLB1, the EPN field
is unused for tlbre. See the EREF for information at the Freescale Book E level.
12.4.1.1 Reading Entries from the TLB1 Array
Entries in TLB1 can be read by first writing the necessary entry-identifying information into
MAS0 using mtspr and then executing the tlbre instruction. To read an entry from TLB1,
MAS0[TLBSEL] must be = 01 and MAS0[ESEL] must be set to point to the desired entry. After
executing the tlbre instruction, MAS0–MAS3 (and optionally, MAS7 for the e500v2) are updated
with the data from the selected TLB entry in TLB1.
12.4.1.2 Reading Entries from the TLB0 Array
Entries in TLB0 can be read by first writing the necessary entry-identifying information into
MAS0 and MAS2 using mtspr and then executing the tlbre instruction. To read an entry from
TLB0, MAS0[TLBSEL] must be = 00, MAS0[ESEL] must be set to point to the desired way, and
EPN[45–51] in MAS2 must be loaded with the desired index. After executing the tlbre
instruction, MAS0–MAS3 (and optionally, MAS7 for the e500v2) are updated with the data from
the selected TLB entry in TLB0.
Summary of Contents for PowerPC e500 Core
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