Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor
3-13
•
Execution of an allocated instruction that causes an auxiliary enabled exception (enabled
exception-type program interrupt).
APUs, such as the SPE, may define additional instruction-caused exceptions and interrupts. The
invocation of an interrupt is precise, except that if one of the imprecise modes for invoking the
floating-point enabled exception-type program interrupt is in effect the invocation of the
floating-point enabled exception-type program interrupt may be imprecise. When the interrupt is
invoked imprecisely, the excepting instruction does not appear to complete before the next
instruction starts (because one of the effects of the excepting instruction, namely the invocation of
the interrupt, has not yet occurred).
Chapter 5, “Interrupts and Exceptions
,” describes interrupt conditions in detail.
3.3
Instruction Set Overview
This section provides a overview of the PowerPC instructions implemented in the e500 and
highlights any special information with respect to how the e500 implements a particular
instruction. Note that some instructions have the following optional features:
•
CR update—The dot (.) suffix on the mnemonic enables the update of the CR.
•
Overflow option—The o suffix indicates that the overflow bit in the XER is enabled.
3.3.1
Book E User-Level Instructions
This section discusses the user-level instructions defined in the Book E architecture.
3.3.1.1
Integer Instructions
This section describes the integer instructions. These consist of the following:
•
Integer arithmetic instructions
•
Integer compare instructions
•
Integer logical instructions
•
Integer rotate and shift instructions
Integer instructions use the content of the GPRs as source operands and place results into GPRs
and the XER and CR fields.
3.3.1.1.1
Integer Arithmetic Instructions
Table 3-6
lists the integer arithmetic instructions for the PowerPC processors.
Summary of Contents for PowerPC e500 Core
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