Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor Part I-1
Part I
e500 Core
Part I specifically describes the e500 core, excluding details about cache memories and MMU
features. It contains chapters that apply to the entire core, as follows:
• Chapter 1, “Core Complex Overview , ” summarizes the e500 core. This a 32-bit
implementation of the Book E PowerPC architecture, including a recognition that different
processor implementations may require extensions or deviations from the architectural
descriptions.
• Chapter 2, “Register Model , ” describes the e500 core register model as defined in Book E
and the additional implementation-specific registers unique to the e500 core, including a
Book E SPR model.
• Chapter 3, “Instruction Model , ” provides information about the Book E architecture as it
relates specifically to the e500 core complex. The e500 core complex also implements
several APUs, which define additional instructions, registers, and interrupts. The chapter
also features operand conventions, branch prediction, memory access alignment support,
and memory synchronization sections.
• Chapter 4, “Execution Timing , ” describes the e500 core’s operations performance as
defined by instructions and how it reports the results of instruction execution. It gives
detailed descriptions of how the core execution units work and how these units interact with
other parts of the processor, such as the instruction fetching mechanism, register files, and
caches. Included are examples of instruction sequences and tables that provide information
useful to assembly language programmers for optimizing performance.
• Chapter 5, “Interrupts and Exceptions , ” is a general description of the Book E interrupt and
exception model and gives details of the additions and changes to that model that are
implemented in the e500 core complex.
• Chapter 6, “Power Management , ” describes the hardware and software resources the
system uses to minimize its power consumption. This chapter regards the power
management facilities as they are defined by Book E and implemented in devices that
contain the e500 core, but its scope is limited to features of the core only.
• Chapter 7, “Performance Monitor , ” describes the e500 implementation of the performance
monitor APU that is defined by the Freescale Book E implementation standards.
• Chapter 8, “Debug Support , ” describes the e500 core complex internal debug capabilities
and associated features. Included are important deviations to the Book E debug mode.