Freescale Semiconductor PowerPC e500 Core, Reference Manual

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L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-27
11.6.2.3 Cache Locking and PLRU
The core complex does not replace locked lines. Each L1 cache line has a lock bit, which can be
set through the cache locking instructions and cleared through the cache unlocking instructions or
line invalidation. Lock bits are used at reload time to steer the PLRU algorithm away from
selecting locked cache lines.
11.7 L2 Cache Support
This section describes interactions between the e500 core and an L2 cache implementation.
11.7.1 Invalidating the L2 Cache after a Cache Tag Parity Error
If an L2 cache tag parity error occurs on an attempt to write a new line, the L2 cache must be flash
invalidated. Performing a dcbi does not invalidate the line because it, like the write, is treated as
a cache miss, so the status of that line is not changed. L2 functionality is not guaranteed if flash
invalidation is not performed after a tag parity error.
See Section 11.4.3, “L1 Instruction and Data Cache Flash Invalidation .”
11.7.2 L2 Locking
The core complex implements specific instructions to selectively lock and unlock lines in its L1
caches or in an L2 cache. To facilitate locking and unlocking of an L2 cache (usually located
directly on the CCB), the core complex provides an address lock attribute (CL) on the bus, which
can be used in conjunction with the transfer type, ttx, encodings to identify which addresses to lock
or unlock.
When the core complex executes an instruction to lock a line in an L2 cache (dcbtls, dcbtstls, or
icbtls, with CT = 1), it normally performs the associated bus operation as a burst read transaction
with a reading-type ttx code (READ, RWITM, or RCLAIM) and with the lock attribute asserted.
An L2 cache may recognize this transaction as a direction to establish the cache line (if not already
valid) and to mark it as locked. Note that this is a complete address/data transaction by the core
complex to memory that requires read data to be returned to the core complex. The read data,
however, is not used or cached internally by the core complex. The purpose for the bus transaction
is to establish a locked line in the L2 cache and to make data available from system memory for
the L2 cache to capture.
If a cache locking instruction targeted at an L2 cache also hits to a line modified in the L1 data
cache, the core complex pushes the line from the L1 data cache as a non-global burst write
operation (similar to a regular L1 castout) with the lock attribute set and the write-through attribute
negated, rather than performing a read bus operation as described above. An L2 cache may also
recognize this transaction as a direction to establish and capture the cache line and mark it as
locked.