Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Performance Monitor
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 7-11
The processor states and the settings of the FCS, FCU, FCM1, and FCM0 fields in PMLCan
necessary to enable monitoring of each processor state are shown in
Table 7-8 .
Two unconditional counting modes may be specified:
• Counting is unconditionally enabled regardless of the states of MSR[PMM] and MSR[PR].
This can be accomplished by clearing PMLCan[FCS], PMLCan[FCU], PMLCan[FCM1],
and PMLCan[FCM0] for each counter control.
• Counting is unconditionally disabled regardless of the states of MSR[PMM] and MSR[PR].
This can be accomplished by setting PMGC0[FAC] or by setting PMLCan[FC] for each
counter control. Alternatively, this can be accomplished by setting PMLCan[FCM1] and
PMLCan[FCM0] for each counter control or by setting PMLCan[FCS] and PMLCan[FCU]
for each counter control.
7.6 Examples
The following sections provide examples of how to use the performance monitor facility:
7.6.1 Chaining Counters
The counter chaining feature can be used to decrease the processing pollution caused by
performance monitor interrupts (such as cache contamination and pipeline effects) by allowing a
higher event count than is possible with a single counter. Chaining two counters together
effectively adds 32 bits to a counter register where the first counter’s overflow event acts like a
carry out feeding the second counter. By defining the event of interest to be another PMC’s
Table 7-8. Processor States and PMLCa0
–
PMLCa3 Bit Settings
Processor State FCS FCU FCM1 FCM0
Marked 0 0 0 1
Not marked 0 0 1 0
Supervisor 0 1 0 0
User 1 0 0 0
Marked and supervisor 0 1 0 1
Marked and user 1 0 0 1
Not marked and supervisor 0 1 1 0
Not mark and user 1 0 1 0
All 0 0 0 0
None X X 1 1
None 1 1 X X