Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-11
3. SRR1 (for noncritical class interrupts) or CSRR1 (for critical class interrupts) or MCSRR1
for machine check interrupts is loaded with a copy of the MSR contents.
4. New MSR values take effect beginning with the first instruction following the interrupt.
The MSR is updated as follows:
— MSR[SPE,WE,EE,PR,FP,FE0,FE1,IS,DS] are cleared by all interrupts.
— MSR[CE,DE] are cleared by critical class interrupts and unchanged by noncritical class
interrupts.
— MSR[ME] is cleared by machine check interrupts and unchanged by other interrupts.
— Other defined MSR bits are unchanged by all interrupts.
MSR fields are described in Section 2.5.1, “Machine State Register (MSR) .”
5. Instruction fetching and execution resumes, using the new MSR value, at a location
specific to the interrupt type (IVPR[32–47] || IVORn[48–59] || 0b0000)
The IVORn for the interrupt type is described in Table 5-6 . IVPR and IVOR contents are
indeterminate upon reset and must be initialized by system software.
Interrupts do not clear reservations obtained with load and reserve instructions. The operating
system should do so at appropriate points, such as at process switch.
At the end of a noncritical interrupt handling routine, executing rfi causes the MSR to be restored
from SRR1 and instruction execution to resume at the address contained in SRR0. Likewise, rfci
and rfmci perform the same function at the end of critical and machine check interrupt handling
routines respectively, using the critical and machine check save/restore registers.
NOTE
In general, at process switch, due to possible process interlocks and
possible data availability requirements, the operating system needs to
consider executing the following:
• stwcx.—Clear outstanding reservations to prevent pairing a lwarx
in the old process with a stwcx. in the new one
• msync—Ensure that memory operations of an interrupted process
complete with respect to other processors before that process
begins executing on another processor
• rfi, rfci, rfmci, or isync—Ensure that instructions in the new
process execute in the new context