Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Memory Management Units
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-21
The address that is used by the processor executing the tlbivax instruction is detailed in
Table 12-5 . Note that this subset address is also the address broadcast to other processors. Thus,
no other information except for that shown in Table 12-5 is used for the invalidation. As shown in
the table, the bits of effective address used to perform the tlbivax invalidation of TLB1, TLB0,
and the L1 TLBs are bits 32–51 of rA + rB.
t
The limited virtual address used to invalidate TLB entries has the side effect that a single tlbivax
instruction can invalidate more than a single entry in a targeted TLB. This is because the tlbivax
does not compare the values of the PID or AS bits. A tlbivax targeted at TLB0 can invalidate either
or both ways within an TLB0 index (for e500v1), up to all four ways for e500v2, and up to all four
ways within an L1TLB4K index. Also, a tlbivax targeted at TLB1 can invalidate up to all 16
entries in the array, or up to all 8 entries of the L1VSPs (instruction and data).
The tlbivax instruction invalidates all matching entries in the instruction and data L1 TLBs
simultaneously. Also, the core complex always snoops TLB invalidate transactions from other
CCB bus masters (if any) and invalidates matching TLB entries accordingly.
Note that entries in TLB1 can be protected from invalidation by the tlbivax instruction by setting
the IPROT bit for those entries. See the EREF for more information on the use of the IPROT bit
defined for Freescale Book E processors.
12.4.4.1 TLB Selection for tlbivax Instruction
Because only a limited subset of the virtual address can be broadcast, extra information about the
targeted TLB entries is encoded in two of the lower bits of the effective address calculated by the
tlbivax instruction. Bit 60 of the tlbivax effective address is interpreted as the TLBSEL field. This
bit indicates whether TLB1 or TLB0 is targeted by the invalidate operation. Because only a few
bits (32–51) of address are broadcast and can be used in the invalidate comparison for TLB1, and
most of those bits are masked out for larger page sizes, the TLBSEL field avoids unnecessary
invalidations of large superpages in TLB1 when the tlbivax is targeting TLB0.
Table 12-5. tlbivax EA Bit Definitions
Bits of (rA + rB)
(preferred form is for rA = 0)
Meaning
More Information
Section/Page
32–51 EA[32–51] for invalidation matching —
52–59 Reserved; should be zero —
60 TLBSEL. Selects which TLB is targeted for invalidation
0 TLB0
1 TLB1 12.4.4.1/12-21
61 INV_ALL command 12.4.4.2/12-22
62–63 Reserved —