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Freescale Semiconductor PowerPC e500 Core, Reference Manual

The Freescale Semiconductor PowerPC e500 Core Reference Manual is a comprehensive guide for users looking to maximize the capabilities of their PowerPC e500 Core processor. This manual can be downloaded for free from manualshive.com, providing users with valuable insights and instructions on how to optimize performance.

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PowerPC e500 Core Family Reference Manual, Rev. 1

Index-8

Freescale Semiconductor

 

M–M

Index

mbar, 3-30, 3-47, 4-17, 13-6
MCAR (machine check address register), 2-22, 5-6, 5-17
mcp input, 5-7

see also Interrupt handling, interrupt types, machine check 

interrupt

MCSR (machine check syndrome register), 2-23, 5-6, 5-7
MCSRR0–1 (machine check save/restore reg’s 0–1), 2-22, 

5-6

Memory management unit (MMU)

address translation (EA to real address), 12-4

page sizes, variable-sized pages (VSPs), 12-6
virtual addresses and PIDs (process IDs), 12-5

features, 12-1
instructions, 12-17–12-24

tlbivax (invalidate), 12-20, 12-21
tlbre (read entry), 12-18
tlbsx (search), 12-19
tlbsync (synchronize), 12-22
tlbwe (write entry), 12-19

overview, 1-24, 1-33
process IDs (PID0–2), 12-5, 12-21
registers, 2-35–2-45, 12-25–12-32

MAS register updates, 12-32
process ID (PID0–2), 12-5, 12-21

TLBs, 12-8–12-25

access times, 4-12, 12-16
consistency between L1, L2 TLB arrays, 12-15
default TLB entries (on reset), 12-24
error on multiple TLB entry hit, 12-8, 12-15
field definitions of TLB entries, 12-17
fields compared to determine a hit, 12-7

access permissions, 12-7

fields on 32-bit Book E implementations, B-2
instructions, 3-41, 11-11
invalidation

invalidate all address encoding, 12-22
invalidate broadcast enabling, 12-22
invalidate selection for tlbivax, 12-21
IPROT (protect from invalidate), 12-12

L1 TLB arrays (not programmable), 12-8

D-L1TLB4K, 12-8
D-L1VSP, 12-8
I-L1TLB4K, 12-8
I-L1VSP, 12-8
replacement algorithm (true LRU), 12-10
structure, 12-9

L2 TLB arrays (programmable), 12-8

replacement algorithm (general), 12-13
replacement algorithm, hints for round robin (TLB0), 

12-13

structure, 12-11
TLB0 (4 Kbyte page sizes), 12-11, 12-18

TLB1 (variable page sizes), 12-11, 12-15, 12-18

maintenance, 12-3, 12-18, 12-22
misses (TLB error interrupts), 12-2, 12-12, 12-20, 12-22

automatic updates, 12-23
handler routines, 12-24

synchronization requirements, 3-6, 3-10
TLB coherency, 1-28
writing to TLB0, 12-19
writing to TLB1, 12-19

Memory model

access ordering, 1-29, 3-45
alignment support, 3-44
atomic updates, 1-29
data organization and transfers, 3-1
reservations, 3-32–3-37, 3-45, 3-48
sequential consistency of accesses, 11-15

and mbar, 3-47, 13-6

synchronization boundary with msync, 3-46, 13-6

Memory subsystem

overview, 1-33

Memory synchronization, 3-30

synchronization instructions, 3-48

Memory/cache access attributes (WIMGE bits), 1-30

caching-inhibited accesses (I bit), 2-42, 11-13

ci  internal signal, 13-2

Endianness (little-endian) bit (E bit), 2-42, 11-13
guarded memory bit (G bit), 2-42

guarded memory, 12-16
speculative accesses, 11-13

L1 caches effects, 11-13
memory coherency required bit (M bit), 2-42, 11-12

gbl  internal signal, 13-3

write-through mode (W bit), 2-42

write-back stores, 11-13
write-through stores, 11-13
wt  internal signal, 13-3

mfmsr, 3-40
mfspr, 3-26
Misaligned accesses, 3-2, 4-49, 11-13
MMUCFG (MMU configuration register), 2-37
MMUCSR0 (MMU control and status register), 2-36
Mnemonics

recommended, C-24
simplified, C-1

MSR (machine state register), 2-10, 5-6

move to/from MSR instructions, 3-40
writing to MSR[EE], 3-40

msync, 3-31, 3-46, 4-17, 13-6
mtmsr, 3-40
mtspr, 3-26

Summary of Contents for PowerPC e500 Core

Page 1: ...PowerPC e500 Core Family Reference Manual Supports e500v1 e500v2 E500CORERM Rev 1 4 2005...

Page 2: ...for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a si...

Page 3: ...Debug Support 8 Part II e500 Core Complex II Timer Facilities 9 Auxiliary Processing Units APUs 10 L1 Caches 11 Memory Management Units 12 Core Complex Bus CCB 13 Appendix A Programming Examples A Ap...

Page 4: ...r 8 Debug Support II Part II e500 Core Complex 9 Timer Facilities 10 Auxiliary Processing Units APUs 11 L1 Caches 12 Memory Management Units 13 Core Complex Bus CCB A Appendix A Programming Examples B...

Page 5: ...Processor and System Version Numbers 1 5 1 3 Features 1 5 1 3 1 e500v2 Differences 1 11 1 4 Instruction Set 1 12 1 5 Instruction Flow 1 14 1 5 1 Initial Instruction Fetch 1 14 1 5 2 Branch Detection...

Page 6: ...13 1 Instruction Set Compatibility 1 32 1 13 1 1 User Instruction Set 1 32 1 13 1 2 Supervisor Instruction Set 1 32 1 13 2 Memory Subsystem 1 33 1 13 3 Exception Handling 1 33 1 13 4 Memory Managemen...

Page 7: ...2 1 Machine Check Save Restore Register 0 MCSRR0 2 22 2 7 2 2 Machine Check Save Restore Register 1 MCSRR1 2 22 2 7 2 3 Machine Check Address Register MCAR 2 22 2 7 2 4 Machine Check Syndrome Register...

Page 8: ...ug Status Register DBSR 2 47 2 13 3 Instruction Address Compare Registers IAC1 IAC4 2 48 2 13 4 Data Address Compare Registers DAC1 DAC2 2 48 2 14 SPE and SPFP APU Registers 2 49 2 14 1 Signal Process...

Page 9: ...Integer Rotate and Shift Instructions 3 16 3 3 1 2 Load and Store Instructions 3 17 3 3 1 2 1 Self Modifying Code 3 17 3 3 1 2 2 Integer Load and Store Address Generation 3 18 3 3 1 2 3 Integer Load...

Page 10: ...cquisition and Import Barriers 3 45 3 5 1 1 Acquire Lock and Import Shared Memory 3 45 3 5 1 2 Obtain Pointer and Import Shared Memory 3 45 3 5 1 3 Lock Release and Export Barriers 3 46 3 5 1 3 1 Expo...

Page 11: ...3 5 Memory Synchronization Timing Considerations 4 17 4 3 5 1 msync Instruction Timing Considerations 4 17 4 3 5 2 mbar Instruction Timing Considerations 4 17 4 4 Execution 4 18 4 4 1 Branch Unit Exe...

Page 12: ...ons 4 47 4 7 6 1 SU Considerations 4 47 4 7 6 2 MU Considerations 4 48 4 7 6 3 LSU Considerations 4 48 4 7 6 3 1 Load Store Interaction 4 48 4 7 6 3 2 Misalignment Effects 4 49 4 7 6 3 3 Load Miss Pip...

Page 13: ...ance Monitor Interrupt 5 33 5 9 Partially Executed Instructions 5 33 5 10 Interrupt Ordering and Masking 5 35 5 10 1 Guidelines for System Software 5 36 5 10 2 Interrupt Order 5 37 5 11 Exception Prio...

Page 14: ...7 Event Selection 7 12 Chapter 8 Debug Support 8 1 Overview 8 1 8 2 Programming Model 8 1 8 2 1 Register Set 8 1 8 2 2 Instruction Set 8 2 8 2 3 Debug Interrupt Model 8 2 8 2 4 Deviations from the Boo...

Page 15: ...ogramming Model 10 2 10 2 1 1 BTB Locking APU Instructions 10 2 10 2 1 2 BTB Locking APU Registers 10 3 10 3 Alternate Time Base APU 10 3 10 3 1 Programming Model 10 3 10 4 Double Precision Floating P...

Page 16: ...struction Cache Coherency Model 11 11 11 3 3 Snoop Signaling 11 12 11 3 4 WIMGE Settings and Effect on L1 Caches 11 13 11 3 4 1 Write Back Stores 11 13 11 3 4 2 Write Through Stores 11 13 11 3 4 3 Cac...

Page 17: ...a Cache Tag Parity Error 11 27 11 7 2 L2 Locking 11 27 11 7 2 1 L2 Unlocking 11 28 11 7 2 2 L1 Overlock 11 28 Chapter 12 Memory Management Units 12 1 e500 MMU Overview 12 1 12 1 1 MMU Features 12 1 1...

Page 18: ...2 4 4 3 TLB Invalidate Broadcast Enabling 12 22 12 4 5 TLB Synchronize tlbsync Instruction 12 22 12 5 TLB Entry Maintenance Details 12 22 12 5 1 Automatic Updates TLB Miss Exceptions 12 23 12 5 2 TLB...

Page 19: ...r 32 Bit Book E B 1 64 Bit Specific Book E Instructions B 1 B 2 Registers on 32 Bit Book E Implementations B 2 B 3 Addressing on 32 Bit Book E Implementations B 2 B 4 TLB Fields on 32 bit Book E Imple...

Page 20: ...nics that Incorporate CR Conditions Listings C 17 C 5 Compare Word Simplified Mnemonics C 20 C 6 Condition Register Logical Simplified Mnemonics C 20 C 7 Trap Instructions Simplified Mnemonics C 21 C...

Page 21: ...ter Upper ATBU 2 17 2 9 Interrupt Vector Offset Registers IVORs 2 19 2 10 Exception Syndrome Register ESR 2 20 2 11 Machine Check Save Restore Register 0 MCSRR0 2 22 2 12 Machine Check Save Restore Re...

Page 22: ...MC3 User Performance Monitor Counter Registers UPMC0 UPMC3 2 57 3 1 Register Indirect with Immediate Index Addressing for Integer Loads Stores 3 18 3 2 Register Indirect with Index Addressing for Inte...

Page 23: ...4 PLRU Replacement Algorithm 11 26 12 1 Effective to Real Address Translation Flow e500v1 12 4 12 2 Effective to Real Address Translation Flow e500v2 12 5 12 3 Virtual Address and TLB Entry Compare Pr...

Page 24: ...PowerPC e500 Core Family Reference Manual Rev 1 xxiv Freescale Semiconductor Figures Figure Number Title Page Number...

Page 25: ...2 9 ESR Field Descriptions 2 21 2 10 MCSR Field Descriptions 2 23 2 11 BBEAR Field Descriptions 2 25 2 12 BBTAR Field Descriptions 2 25 2 13 BUCSR Field Descriptions 2 26 2 14 HID0 Field Descriptions...

Page 26: ...on Requirements 3 9 3 6 Integer Arithmetic Instructions 3 14 3 7 Integer 32 Bit Compare Instructions L 0 3 15 3 8 Integer Logical Instructions 3 15 3 9 Integer Rotate Instructions 3 16 3 10 Integer Sh...

Page 27: ...es 4 31 4 4 System Operation Instruction Execution Latencies 4 31 4 5 Condition Register Logical Execution Latencies 4 33 4 6 SU and MU PowerPC Instruction Execution Latencies 4 33 4 7 LSU Instruction...

Page 28: ...ettings 5 31 5 30 Embedded Floating Point Data Interrupt Register Settings 5 32 5 31 Embedded Floating Point Round Interrupt Register Settings 5 33 5 32 Operations to Avoid 5 36 6 1 Power Management S...

Page 29: ...12 10 MAS2 Field Descriptions EPN and Page Attributes 12 28 12 11 MAS3 Field Descriptions RPN and Access Control 12 29 12 12 MAS4 Field Descriptions Hardware Replacement Assist Configuration 12 30 12...

Page 30: ...Simplified Mnemonics for bcl and bcla with Comparison Conditions and LR Updating C 18 C 22 Simplified Mnemonics for bclrl and bcctrl with Comparison Conditions and LR Updating C 19 C 23 Word Compare S...

Page 31: ...llows The Book E architecture Book E defines a set of user level instructions and registers that are drawn from the user instruction set architecture UISA portion of the AIM definition PowerPC archite...

Page 32: ...issues executed and completed and how instruction results are presented to the processor and memory system Tables are provided that indicate latency and throughput for each of the instructions support...

Page 33: ...ics for PowerPC Instructions provides a set of simplified mnemonic examples and symbols Appendix D Opcode Listings lists opcodes by mnemonic and by opcode It includes an alphabetical listing that incl...

Page 34: ...Hardware specifications Hardware specifications provide specific data regarding bus timing signal behavior and AC DC and thermal characteristics as well as other design considerations Product briefs E...

Page 35: ...e NOT logical operator AND logical operator OR logical operator Indicates reserved bits or bit fields in a register Although these bits can be written to as ones or zeros they are always read as zeros...

Page 36: ...PowerPC e500 Core Family Reference Manual Rev 1 xxxvi Freescale Semiconductor...

Page 37: ...he e500 core s operations performance as defined by instructions and how it reports the results of instruction execution It gives detailed descriptions of how the core execution units work and how the...

Page 38: ...PowerPC e500 Core Family Reference Manual Rev 1 Part I 2 Freescale Semiconductor...

Page 39: ...summary of the Book E architecture compatibility and migration from the original version of the PowerPC architecture as it is defined by Apple IBM and Motorola referred to as the AIM version of the Po...

Page 40: ...Issue Queue BIQ TLB0 TLB Array TLB1 Register Unified L1 Data MMU 64 Entry D L1TLB4K 4 Entry D L1VSP Two Instruction Dispatch 1 BIQ 2 GIQ Core Interface Unit L1 Instruction MMU 64 Entry I L1TLB4K 4 En...

Page 41: ...unctionality is implemented in all PowerQUICC III devices However these instructions will not be supported in devices subsequent to PowerQUICC III Freescale Semiconductor strongly recommends that use...

Page 42: ...support 4 Kbyte pages These arrays are maintained entirely by the hardware with a true least recently used LRU algorithm The second level MMU contains a 16 entry fully associative unified instruction...

Page 43: ...r facility provides the ability to monitor and count predefined events such as processor clocks misses in the instruction cache or data cache types of instructions decoded or mispredicted branches The...

Page 44: ...d to 64 bits to support 64 bit load store and merge operations Note that the upper 32 bits are affected only by 64 bit instructions A 64 bit accumulator ACC has been added The signal processing and em...

Page 45: ...of interlocks Decodes as many as two instructions per cycle Decode serialization control Register dependency resolution and renaming Branch prediction unit BPU Dynamic branch prediction using a 512 e...

Page 46: ...divide instructions If rA or rB is zero floating point divide instructions take 4 cycles all others take 29 Note that although most divide instructions take more than 4 cycles to execute the MU allow...

Page 47: ...in some implementations Bus support for hardware enforced coherency bus snooping Core complex bus CCB internal bus High speed on chip local bus with data tagging 32 bit address bus Address protocol w...

Page 48: ...for the e500v1 and 4 Kbyte 4 Gbyte pages for the e500v2 and fixed size 4 Kbyte pages Data L1 MMU 4 entry fully associative TLB array for variable sized pages 64 entry 4 way set associative TLB for 4...

Page 49: ...itional features not supported by the e500v1 The e500v2 uses 36 bit physical addressing which is supported by the following MMU assist register 7 MAS7 HID0 EN_MAS7_UPDATE Programmable jumper options t...

Page 50: ...e500 supports the following implementation specific instructions Integer select APU This APU consists of the Integer Select instruction isel which functions as an if then else statement that selects...

Page 51: ...ed Integer efscfsi efdcfsi evfscfsi rD rB Convert Floating Point from Unsigned Fraction efscfuf efdcfuf evfscfuf rD rB Convert Floating Point from Unsigned Integer efscfui efdcfui evfscfui rD rB Conve...

Page 52: ...ructions using both the lower and upper halves of the 64 bit GPRs The parallel execution units allow multiple instructions to execute in parallel and out of order For example a low latency addition in...

Page 53: ...t streams are allowed to execute and proceed through the completion queue although they can complete only after the branch prediction is resolved as correct and after the branch instruction itself com...

Page 54: ...tion is in the on chip instruction cache or an L2 cache if implemented Those factors increase when it is necessary to fetch instructions from system memory and include the processor to bus clock ratio...

Page 55: ...that are assigned a space in the CQ but not in an issue queue Dispatch is treated as an event at the end of the decode stage The issue stage reads source operands from rename registers and register fi...

Page 56: ...ng an exception status or a mispredicted branch all following instructions are cancelled their execution results in rename registers are discarded and the correct instruction stream is fetched The com...

Page 57: ...RR0 Critical SRR 0 1 Processor version spr 528 IVOR32 1 Interrupt vector offset registers 32 35 spr 287 PVR spr 59 CSRR1 spr 529 IVOR33 1 Timer Decrementer Registers spr 570 MCSRR0 1 Machine check SRR...

Page 58: ...etting L1CSR0 CFI the entire instruction cache can be invalidated by setting L1CSR1 ICFI 1 8 Interrupts and Exception Handling The e500 core supports an extended exception handling model with nested i...

Page 59: ...zing mechanism the address in the appropriate save restore register is the address of the interrupt forcing instruction If the interrupt was not caused by either of those mechanisms the address in the...

Page 60: ...ase the latency is indeterminate The minimum latency is 3 core clocks and the maximum is 8 not including the 2 bus clock cycles required to synchronize the interrupt signal from the pad When an interr...

Page 61: ...ation on machine check interrupts and restores machine state after an rfmci instruction is executed ESR Exception syndrome register Provides a syndrome to differentiate between the different kinds of...

Page 62: ...ough required W Caching inhibited I Memory coherency required M Guarded G Endianness E User definable U0 U3 a 4 bit implementation specific field The core complex employs a two level memory management...

Page 63: ...2 TLB array TLB1 that supports all nine variable page sizes TLB array TLB0 that supports only 4 Kbyte pages as follows e500v1 256 entry 2 way set associative TLB array e500v2 512 entry 4 way set assoc...

Page 64: ...t virtual address Figure 1 9 shows the translation flow for the e500v1 core Figure 1 9 Effective to Real Address Translation Flow Effective Page Number Byte Address Real Page Number Byte Address 32 bi...

Page 65: ...rts using a true LRU algorithm 1 9 2 MMU Assist Registers MAS0 MAS4 and MAS6 MAS7 Book E defines SPR numbers for the MMU assist registers which are used to hold values either read from or to be writte...

Page 66: ...MMU The lookup is specified by the instruction encoding and specific search fields in MAS6 The values placed in the MAS registers may differ depending on a successful or unsuccessful search For TLB m...

Page 67: ...ionality The processor revokes reservations during a context switch so the programmer must reacquire the reservation after a context switch occurs 1 10 2 Memory Access Ordering The core complex suppor...

Page 68: ...wo different sources simultaneously and all three data buses may be operated concurrently The address in bus supports snooping for external management of the L1 caches and TLBs by other bus masters Th...

Page 69: ...ollowing conditions are met A counter is in the overflow state The counter s overflow signaling is enabled Overflow exception generation is enabled in PMGC0 MSR EE is set 1 12 3 Local Control Register...

Page 70: ...1 Instruction Set Compatibility The following sections generally describe the user and supervisor instruction sets 1 13 1 1 User Instruction Set The e500 core executes legacy user mode binaries and ob...

Page 71: ...efined in the OEA to provide compatibility Unlike the AIM version of the PowerPC architecture Book E does not define a reset vector execution begins at a fixed virtual address 0xFFFF_FFFC Some Book E...

Page 72: ...otection mechanisms Unlike the AIM version of the PowerPC core as soon as instruction fetching begins the e500 core is in virtual mode with a hardware initialized TLB entry EIS defined aspects of the...

Page 73: ...mplemented on the device 2 1 Overview Although this chapter organizes registers according to their functionality they can be differentiated according to how they are accessed as follows General purpos...

Page 74: ...registers Book E defined registers that are accessed as part of instruction execution These include the following Registers used for integer operations General purpose registers GPRs Book E defines a...

Page 75: ...tical SRR 0 1 Processor version spr 528 IVOR32 1 Interrupt vector offset registers 32 35 spr 287 PVR spr 59 CSRR1 spr 529 IVOR33 1 Timer Decrementer Registers spr 570 MCSRR0 1 Machine check SRR 0 1 sp...

Page 76: ...2 8 Software Use SPRs SPRG0 SPRG7 and USPRG0 Section 2 9 Branch Target Buffer BTB Registers Section 2 10 Hardware Implementation Dependent Registers Section 2 11 L1 Cache Configuration Registers Secti...

Page 77: ...ause a principal goal of the Book E architecture is to offer flexibility among embedded processors and families of embedded processors some resources are either defined as optional or are defined in a...

Page 78: ...SR Exception syndrome register 62 00001 11110 Read Write Yes 2 7 1 6 2 20 IAC1 Instruction address compare 1 312 01001 11000 Read Write Yes 2 13 3 2 48 IAC2 Instruction address compare 2 313 01001 110...

Page 79: ...18 TBL Time base lower 268 01000 01100 Read only No 2 6 3 2 16 284 01000 11100 Write only Yes 2 6 3 2 16 TBU Time base upper 269 01000 01101 Read only No 2 6 3 2 16 285 01000 11101 Write only Yes 2 6...

Page 80: ...register 1 516 Read only No 2 11 4 2 35 L1CSR0 L1 cache control and status register 0 1 1010 Read Write Yes 2 11 1 2 31 L1CSR1 L1 cache control and status register 1 1 1011 Read Write Yes 2 11 2 2 33...

Page 81: ...ation of an instruction considered as a whole not on intermediate results For example the Subtract from Carrying instruction subfc the result of which is specified as the sum of three values sets bits...

Page 82: ...e 2 2 defines the state of the processor that is enabling and disabling of interrupts and debugging exceptions enabling and disabling of address translation for instruction and data memory accesses en...

Page 83: ...uctions that access the upper half of the 64 bit GPRs 39 44 Reserved should be cleared 1 45 WE Wait state enable On the e500 this allows the core complex to signal a request for power management accor...

Page 84: ...enabled 54 DE Debug interrupt enable 0 Debug interrupts are disabled 1 Debug interrupts are enabled if DBCR0 IDM 1 For the e500 see the description of the DBSR UDE in Section 2 13 2 Debug Status Regi...

Page 85: ...Revision W Reset e500v1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset e500v2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 2 3 Processor Version Regis...

Page 86: ...e software timer The time base for the TB and DEC is selected by the time base enable TBEN and select time base clock SEL_TBCLK bits in HID0 as follows If HID0 TBEN 1 and HID0 SEL_TBCLK 0 the time bas...

Page 87: ...FIE ARE WPEXT FPEXT W Reset All zeros Figure 2 6 Timer Control Register TCR Table 2 5 TCR Implementation Specific Field Descriptions Bits Name Description 32 33 WP Watchdog timer period When concaten...

Page 88: ...one of the following occurs DEC is altered by software in the interim The TB update frequency changes DEC is typically used as a general purpose software timer The decrementer auto reload register is...

Page 89: ...is accessible in both user and supervisor mode Table 2 7 describes the ATBU fields 2 7 Interrupt Registers Section 2 7 1 Interrupt Registers Defined by Book E and Section 2 7 2 e500 Specific Interrupt...

Page 90: ...hen rfi executes SRR1 contents are placed into MSR SRR1 bits that correspond to reserved MSR bits are also reserved These registers are not affected by rfci or rfmci Reserved MSR bits may be altered b...

Page 91: ...rrupt type Table 2 8 shows the IVORs implemented on the e500 IVOR0 IVOR15 are defined by the architecture Note that the e500 does not implement IVOR7 and IVOR9 In addition IVOR32 IVOR35 SPR 528 531 ar...

Page 92: ...se the ESR for machine check interrupts but instead uses the machine check syndrome register MCSR described in Section 2 7 2 4 Machine Check Syndrome Register MCSR The ESR is defined in Book E but dif...

Page 93: ...39 Not supported on the e500 Defined by Book E as FP floating point operations On the e500 this bit is reserved and permanently cleared indicating that the e500 does not implement a Book E FPU Setting...

Page 94: ...achine check interrupt is taken MSR contents are placed into MCSRR1 shown in Figure 2 12 When rfmci executes MCSRR1 contents are restored to MSR MCSRR1 bits that correspond to reserved MSR bits are al...

Page 95: ...corresponding module The MCSR is shown in Figure 2 14 Table 2 10 describes the MCSR fields SPR 572 Access Supervisor only 32 33 34 35 36 39 R MCP ICPERR DCP_PERR DCPERR W Reset All zeros 40 47 R W Re...

Page 96: ...ster can be accessed in supervisor or user mode 2 9 Branch Target Buffer BTB Registers SPRs are defined in the core complex for enabling the locking and unlocking of entries in the BTB These are calle...

Page 97: ...ve entry address bits 0 29 62 63 IAB 0 1 Instruction after branch with BBTAR 62 3 bit pointer that points to the instruction in the cache block after the branch If the branch is the last instruction i...

Page 98: ...FI flash clears the valid bit of all entries in the branch buffer clearing occurs independently from the value of the enable bit BPEN BBFI is always read as 0 55 BBLO Branch buffer lock overflow statu...

Page 99: ...onization as described in Section 2 16 Synchronization Requirements for SPRs Table 2 14 describes the HID0 fields SPR 1008 Access Supervisor only 32 33 39 40 41 42 43 47 R EMCP DOZE NAP SLEEP W Reset...

Page 100: ...tlbre and tlbsx 0 MAS7 is not updated by a tlbre or tlbsx 1 MAS7 is updated by a tlbre or tlbsx 57 DCFA Data cache flush assist e500v2 only Force data cache to ignore invalid sets on miss replacement...

Page 101: ...r to the Register Summary chapter in the device s reference manual HID1 is used for bus configuration and control Writing to HID1 requires synchronization as described in Section 2 16 Synchronization...

Page 102: ...n is taken immediately and processing does not continue with potentially bad data However setting RFXE when a peripheral block is configured to also signal an interrupt for a core_fault_in case result...

Page 103: ...dcbf mbar msync tlbivax tlbsync icbi based on ABE On some implementations ABE must be set to allow management of external L2 caches 0 Address broadcasting disabled 1 Address broadcasting enabled 52 R...

Page 104: ...tered a dcbi snoop that invalidated a locked line 1 The cache has encountered a dcbi snoop that invalidated a locked line 53 CUL Data Cache unable to lock Sticky bit set by hardware and cleared by wri...

Page 105: ...must also be enabled ICPE 1 when this bit is set Note that if the programmer attempts to set L1CSR1 ICPI using mtspr without setting L1CSR1 ICPE L1CSR1 ICPI will not be set enforced by hardware 49 51...

Page 106: ...cessed or updated 1 Enables instruction cache operation SPR 515 Access Supervisor read only 32 33 34 38 39 40 41 42 43 44 45 49 50 51 52 53 55 56 63 R CARCH CBSIZE CREPL CLA CPA CNWAY CSIZE W Reset 0...

Page 107: ...ZE Cache size 0x20 indicates 32 Kbytes SPR 516 Access Supervisor read only 32 38 39 40 41 42 43 44 45 52 53 63 R ICBSIZE ICREPL ICLA ICPA ICNWAY ICSIZE W Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1...

Page 108: ...and L2 MMUs Writing to MMUCSR0 requires synchronization as described in Section 2 16 Synchronization Requirements for SPRs Table 2 20 describes the MMUCSR0 fields SPR SPR SPR 48 PID0 PID in Book E 633...

Page 109: ...ers A 4 bit field that indicates the number of PID registers provided by the processor The e500 implements three PIDs 53 57 PIDSIZE PID register size The 5 bit value of PIDSIZE is one less than the nu...

Page 110: ...0 0 0 0 0 Figure 2 27 TLB Configuration Register 0 TLB0CFG Table 2 22 TLB0CFG Field Descriptions Bits Name Description 32 39 ASSOC Associativity of TLB0 0x02 Indicates associativity is 2 way set assoc...

Page 111: ...3 R ASSOC MINSIZE MAXSIZE IPROT AVAIL NENTRY W Reset e500v1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset e500v2 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0...

Page 112: ...LB as follows When TLBSEL 00 TLB0 selected bits 46 47 are used and bits 44 45 should be cleared This field selects between way 0 1 2 or 3 of TLB0 EA bits 45 51 from MAS2 EPN are used to index into the...

Page 113: ...rays that support invalidate protection are denoted as such in the TLB configuration registers 0 Entry is not protected from invalidation 1 Entry is protected from invalidation 34 39 Reserved should b...

Page 114: ...Caching inhibited 0 Accesses to this page are considered cacheable 1 The page is considered caching inhibited All loads and stores to the page bypass the caches and are performed directly to main mem...

Page 115: ...s Name Description 32 51 RPN Real page number Depending on page size only the bits associated with a page boundary are valid Bits that represent offsets within a page are ignored and should be zero No...

Page 116: ...on The e500 implementation defines bits 44 45 as reserved and bits 46 47 as follows 00 PID0 01 PID1 10 PID2 11 TIDZ 0x00 all zeros 48 51 Reserved should be cleared 52 55 TSIZED Default TSIZE value Spe...

Page 117: ...or These registers are intended for use by special debug tools and debug software and not by general application or operating system code Table 2 29 MAS6 Field Descriptions Bits Name Description 32 39...

Page 118: ...uires synchronization as described in Section 2 16 Synchronization Requirements for SPRs Table 2 32 describes the DBCR1 fields Table 2 31 DBCR0 Field Descriptions Bits Name Description 34 35 RST Reset...

Page 119: ...le 2 34 DBSR UDE The MRR field is affected by the e500 definition of the HRESET signal as defined in Table 2 34 SPR 310 Access Supervisor only 32 33 34 35 36 37 38 39 40 41 42 63 R DAC1US DAC1ER DAC2U...

Page 120: ...s Compare Registers DAC1 DAC2 The e500 implements the DAC1 and DAC2 as they are defined by the Book E architecture A debug event may be enabled to occur upon loads stores or cache operations to an add...

Page 121: ...PowerQUICC III Freescale Semiconductor strongly recommends that use of these instructions be confined to libraries and device drivers Customer software that uses SPE or embedded floating point APU in...

Page 122: ...undefined if the processor takes a floating point exception due to input error floating point overflow or floating point underflow 35 FXH Embedded floating point sticky bit high Floating bit from the...

Page 123: ...dividend and divisor are zero 53 FDBZ Embedded floating point divide by zero error Set if the dividend is non zero and the divisor is zero 54 FUNF Embedded floating point underflow error 55 FOVF Embed...

Page 124: ...urces used exclusively by the performance monitor PMRs are similar to the SPRs defined in the Book E architecture and are accessed by mtpmr and mfpmr which are also defined by the EIS Table 2 36 lists...

Page 125: ...0 2 15 4 2 56 UPMLCa1 User performance monitor local control a1 129 00100 00001 UPMLCa2 User performance monitor local control a2 130 00100 00010 UPMLCa3 User performance monitor local control a3 131...

Page 126: ...nt occurs when the selected bit changes from 0 to 1 e500v2 only 00 TB 63 TBL 31 01 TB 55 TBL 23 10 TB 51 TBL 19 11 TB 47 TBL 15 Time base transition events can be used to periodically collect informat...

Page 127: ...ter 0 The PMC is incremented if permitted by other PM control bits 1 The PMC is not incremented 33 FCS Freeze counter in supervisor state 0 The PMC is incremented if permitted by other PM control bits...

Page 128: ...le 2 40 PMLCb0 PMLCb3 Field Descriptions Bits Name Description 32 52 Reserved should be cleared 53 55 THRESHMUL Threshold multiple 000 Threshold field is multiplied by 1 PMLCbn THRESHOLD 1 001 Thresho...

Page 129: ...le MSR EE is zero is not taken until MSR EE is set Setting PMGC0 FCECE forces counters to stop counting when an enabled condition or event occurs Software is expected to use mtpmr to explicitly set PM...

Page 130: ...for these SPRs there are no synchronization requirements for accessing SPRs beyond those stated in Book E Table 2 42 Synchronization Requirements for SPRs Registers Instruction Instruction Required B...

Page 131: ...pter 10 Auxiliary Processing Units APUs Specific information about how these instructions are executed is provided in Chapter 4 Execution Timing 3 1 Operand Conventions This section describes operand...

Page 132: ...te that lmw stmw lwarx and stwcx instructions that are not word aligned cause an alignment exception 3 1 3 e500 Floating Point Implementation The e500 does not implement the floating point instruction...

Page 133: ...tions Freescale will also provide libraries to support next generation PowerQUICC devices 3 1 4 Unsupported Book E Instructions Because the e500 core complex uses a 32 bit Book E core all of the instr...

Page 134: ...d CR fmul s Floating Negative Absolute Value and record CR fnabs Floating Negate and record CR fneg Floating Negative Multiply Add Single and record CR fnmadd s Floating Negative Multiply Subtract Sin...

Page 135: ...ons Memory synchronization instructions These instructions are used for memory synchronizing See Section 3 3 1 6 Memory Synchronization Instructions Memory control instructions These instructions prov...

Page 136: ...s Preserved instructions Reserved illegal or no op instructions These classes are defined in the Instruction Model chapter of the EREF The class is determined by examining the primary opcode and any e...

Page 137: ...context altering instruction should be interpreted as meaning the context altering instruction itself The synchronizing instruction before the context altering instruction ensures that all instructio...

Page 138: ...efore may not be context synchronizing mtmsr DS None CSI 1 mtmsr WE msync isync 3 3 See Section 6 4 1 Software Considerations for Power Management mtspr DAC1 DAC2 4 4 Synchronization requirements for...

Page 139: ...synchronizing instruction that is sc isync rfci or rfi Table 3 5 Instruction Fetch and or Execution Synchronization Requirements Context Altering Instruction or Event Required Before Required After N...

Page 140: ...may not be context synchronizing 4 CSI indicates any context synchronizing instruction that is sc isync rfci rfmci or rfi 5 Synchronization requirements for changing the wait state enable are implemen...

Page 141: ...l address space and memory protection in which they were initiated 3 If the operation directly causes an interrupt for example sc directly causes a system call interrupt or is an interrupt the operati...

Page 142: ...rrupt An attempt by an application program to access a privileged SPR privileged instruction exception type program interrupt An attempt by an application program to access an SPR that does not exist...

Page 143: ...errupt conditions in detail 3 3 Instruction Set Overview This section provides a overview of the PowerPC instructions implemented in the e500 and highlights any special information with respect to how...

Page 144: ...tion of a 32 bit result only if the instruction s OE bit is set Table 3 6 Integer Arithmetic Instructions Name Mnemonic Syntax Add add add addo addo rD rA rB Add Carrying addc addc addco addco rD rA r...

Page 145: ...ctions The logical instructions shown in Table 3 8 perform bit parallel operations on the specified operands Logical instructions with the CR updating enabled uses dot suffix and instructions andi and...

Page 146: ...s are obtained by specifying masks and shift values for certain rotate instructions Simplified mnemonics shown in Appendix C Simplified Mnemonics for PowerPC Instructions are provided to simplify codi...

Page 147: ...t cross a double word boundary degrade performance Although many misaligned memory accesses are supported in hardware the frequent use of them is discouraged because they can compromise the overall pe...

Page 148: ...hes 3 3 1 2 2 Integer Load and Store Address Generation Integer load and store operations generate effective addresses using register indirect with immediate index mode register indirect with index mo...

Page 149: ...instruction descriptions as rA 0 Figure 3 2 shows how an effective address is generated using this addressing mode Figure 3 2 Register Indirect with Index Addressing for Integer Loads Stores Register...

Page 150: ...structions Name Mnemonic Syntax Load Byte and Zero lbz rD d rA Load Byte and Zero Indexed lbzx rD rA rB Load Byte and Zero with Update lbzu rD d rA Load Byte and Zero with Update Indexed lbzux rD rA r...

Page 151: ...e page is marked cacheable write through WIM 10x but as with other memory accesses data storage interrupts can result for other reasons such as protection violations or page faults 3 3 1 2 4 Integer S...

Page 152: ...structions is interrupted it may be restarted requiring multiple memory accesses The Book E architecture defines the Load Multiple Word lmw instruction with rA in the range of registers to be loaded a...

Page 153: ...O operand is ignored for branch prediction The e500 instead implements dynamic branch prediction as part of the branch table buffer BTB described in Section 4 4 1 Branch Unit Execution The encodings f...

Page 154: ...simplified mnemonics and symbols is provided for the most frequently used forms of branch conditional compare trap rotate and shift and certain other instructions see Appendix C Simplified Mnemonics...

Page 155: ...e trap instructions shown in Table 3 19 test for a specified set of conditions If any of the conditions tested by a trap instruction are met the system trap type program interrupt is taken For more in...

Page 156: ...izes the instructions for reading from or writing to the CR Implementation Note The Book E architecture states that the Move to Condition Register Fields mtcrf instruction can perform more slowly when...

Page 157: ...ompare 1 312 01001 11000 Read Write Yes 2 13 3 2 48 IAC2 Instruction address compare 2 313 01001 11001 Read Write Yes 2 13 3 2 48 IVOR0 Critical input 400 01100 10000 Read Write Yes 2 7 1 5 2 19 IVOR1...

Page 158: ...ower 268 01000 01100 Read only No 2 6 3 2 16 284 01000 11100 Write only Yes 2 6 3 2 16 TBU Time base upper 269 01000 01101 Read only No 2 6 3 2 16 285 01000 11101 Write only Yes 2 6 3 2 16 TCR Timer c...

Page 159: ...4 2 35 L1CSR0 L1 cache control and status register 0 1010 Read Write Yes 2 11 1 2 31 L1CSR1 L1 cache control and status register 1 1011 Read Write Yes 2 11 2 2 33 MAS0 MMU assist register 0 624 Read W...

Page 160: ...tests selected CRn EQ and even if the branch target is the next sequential instruction to be executed Load Word and Reserve Indexed lwarx rD rA rB lwarx with stwcx can emulate semaphore operations suc...

Page 161: ...el conditions Frequent use of msync degrades performance System designs with an external cache should take care to recognize the hardware signaling caused by an MSYNC bus operation and perform the app...

Page 162: ...altered only by stores that are in the same set for both cases described above For the second use mbar MO 1 can be thought of as placing a barrier into the stream of memory accesses issued by a core s...

Page 163: ...x The stwcx is a store to a word aligned location that is conditioned on the existence of the reservation created by the lwarx and on whether both instructions specify the same location To emulate an...

Page 164: ...and swap primitive like that provided by the IBM System 370 compare and swap instruction which checks only that the old and current values of the word being tested are equal with the result that progr...

Page 165: ...ntended to be paired must be scrupulously avoided For example there must not be a context switch in which the processor holds a reservation on behalf of the old context and the new context resumes aft...

Page 166: ...context switches It may also include implementation dependent causes of reservation loss An implementation may make a forward progress guarantee defining the conditions under which the system as a who...

Page 167: ...ons The instructions listed in Table 3 26 help user level programs manage on chip caches if they are implemented See Chapter 11 L1 Caches for more information about cache topics The following sections...

Page 168: ...formed and the cache block is marked modified However if the replacement block is marked modified the contents are written back to memory first dcbz takes an alignment interrupt if the cache is locked...

Page 169: ...in the L2 cache In this case dcbtst reloads the L1 data cache with the state found in the L2 cache Again if the block was in the shared state in the L2 a subsequent store hits on this shared block an...

Page 170: ...Syntax Implementation Notes Return from Interrupt rfi rfi is context synchronizing which for the e500 means it works its way to the final execute stage updates architected registers and redirects the...

Page 171: ...ation Notes TLB Invalidate Virtual Address Indexed tlbivax rA rB A TLB invalidate operation is performed whenever tlbivax is executed tlbivax invalidates any TLB entry that corresponds to the virtual...

Page 172: ...if RA 0 then generate exception EA 32 0 GPR RB 32 63 ProcessID MAS6 SPID 0b0000_0000 AS MAS6 SAS VA AS ProcessID EA if Valid_TLB_matching_entry_exists VA then result see Table 12 15 column tlbsx hit e...

Page 173: ...s are listed in Table 3 36 and Table 3 37 Table 3 31 Implementation Specific Instructions Summary Name Mnemonic Syntax Category TLB Invalidate Virtual Address Indexed tlbivax rA rB These are described...

Page 174: ...uiring a cache access A word or half word memory access requires multiple accesses if it crosses a double word boundary but not if it crosses a natural boundary Vector loads and stores cause alignment...

Page 175: ...y placing an isync instruction immediately following the loop containing the lwarx and stwcx The following example uses the Compare and Swap primitive to acquire the lock In this example it is assumed...

Page 176: ...n instruction or sequence of instructions that prevents the store that releases a lock from being performed before stores caused by instructions preceding the barrier have been performed An export bar...

Page 177: ...ds the store that releases the lock could be performed before those loads If it is necessary to ensure that those loads are performed before the store that releases the lock the programmer can either...

Page 178: ...MO 1 the EIS defines mbar to function identically to the Classic PowerPC architecture definition of eieio If MO is not 1 the e500 executes mbar as though MO 0 The e500 core complex implements lwarx an...

Page 179: ...registers as containing two 32 bit elements or four 16 bit elements as described in Section 3 8 1 3 SPE APU Instructions However like 32 bit Book E instructions scalar SPFP APU floating point instruct...

Page 180: ...Machine state Single prec Single prec Interrupt Registers Single prec Single prec spr 62 ESR SPE Exception syndrome Single prec Single prec Interrupt Vector Offset Registers spr 405 IVOR5 Alignment A...

Page 181: ...hese instructions can be found in the Instruction Set chapter of the EREF 3 8 1 1 SPE Operands Signed Fractions In signed fractional format the N bit operand is represented in a 1 N 1 format 1 sign bi...

Page 182: ...identical for unsigned operands Table 3 34 shows how SPE APU vector multiply instruction mnemonics are structured Table 3 34 SPE APU Vector Multiply Instruction Mnemonic Structure Prefix Multiply Ele...

Page 183: ...aaw Add to accumulator words Add word results to accumulator words pair of 32 bit sums an Add negated Add negated result to accumulator 64 bit sum anw Add negated to accumulator words Add negated word...

Page 184: ...Vector Compare Less Than Unsigned evcmpltu crD rA rB Vector Convert Floating Point to Unsigned Integer with Round toward Zero evfsctuiz rD rB Vector Count Leading Sign Bits Word evcntlsw rD rA Vector...

Page 185: ...dulo Integer evmhesmi rD rA rB Vector Multiply Half Words Even Signed Modulo Integer and Accumulate into Words evmhesmiaaw rD rA rB Vector Multiply Half Words Even Signed Modulo Integer and Accumulate...

Page 186: ...e into Words evmhoumiaaw rD rA rB Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate Negative into Words evmhoumianw rD rA rB Vector Multiply Half Words Odd Unsigned Modulo Integer...

Page 187: ...tor Multiply Word Signed Saturate Fractional and Accumulate 3 evmwssfaa rD rA rB Vector Multiply Word Signed Saturate Fractional and Accumulate Negative 3 evmwssfan rD rA rB Vector Multiply Word Unsig...

Page 188: ...Store Word of Word from Odd evstwwo rS d rA Vector Store Word of Word from Odd Indexed evstwwox rS rA rB Vector Subtract from Word evsubfw rD rA rB Vector Subtract Immediate from Word evsubifw rD UIM...

Page 189: ...rt Floating Point from Unsigned Fraction efscfuf efdcfuf evfscfuf rD rB Convert Floating Point from Unsigned Integer efscfui efdcfui evfscfui rD rB Convert Floating Point Single from Double Precision...

Page 190: ...int Test Less Than efststlt efdtstlt evfststlt crD rA rB SPE Double Word Load Store Instructions Vector Load Double Word into Double Word evldd rD d rA Vector Load Double Word into Double Word Indexed...

Page 191: ...d the block is already in the L2 cache dcbtls marks the block so it is not a candidate for replacement Data Cache Block Touch for Store and Lock Set dcbtstls CT rA rB If CT 0 the e500 core fetches the...

Page 192: ...n index in which all cache ways are already locked the least recently used way is evicted and L1CSR0 CLO is set indicating an overlock the new line is not locked or cached To precisely detect an overl...

Page 193: ...the target instruction of the 512 most recently taken branches Table 3 43 lists the BTB instructions The branch buffer entry address register BBEAR and the branch buffer target address register BBTAR...

Page 194: ...ess or if the entry exists but it is not locked the instruction is a no op and no other status is reported After bbelr executes the entry continues to be valid in the BTB with all its attributes uncha...

Page 195: ...he address in the BBEAR the target address of that entry is overwritten with the target address in the BBTAR and BUCSR BBLO is set If all the ways of the BTB are locked for the index to which the BBEA...

Page 196: ...k E PowerPC AIM e500 addc o evmwsmiaa SPE APU adde o evmwsmian SPE APU addi evmwssf SPE APU addic evmwssfa SPE APU addis evmwssfaa SPE APU addme o evmwssfan SPE APU add o evmwumi SPE APU addze o evmwu...

Page 197: ...PU dcbtstls Cache locking extsb dcbz extsh divw o extsw 64 bit only divwu o fabs eciwx fadds ecowx fadd efdabs DPFP e500v2 fcfid efdadd DPFP e500v2 fcmpo efdcfs DPFP e500v2 efdcfsf DPFP e500v2 fcmpu e...

Page 198: ...king efscmplt Scalar SPFP icbt efsctsf Scalar SPFP icbtls Cache locking efsctsi Scalar SPFP isel Integer select efsctsiz Scalar SPFP isync efsctuf Scalar SPFP lbz efsctui Scalar SPFP lbzu efsctuiz Sca...

Page 199: ...PFP lwzux evfscfsi Vector SPFP lwzx evfscfuf Vector SPFP mbar evfscfui Vector SPFP mcrf evfscmpeq Vector SPFP mcrfs evfscmpgt Vector SPFP mcrxr evfscmplt Vector SPFP mfapidi evfsctsf Vector SPFP mfcr...

Page 200: ...vlwhosx SPE APU mulldo evlwhou SPE APU mulli evlwhoux SPE APU mullw o evlwhsplat SPE APU nand evlwhsplatx SPE APU neg o evlwwsplat SPE APU nor evlwwsplatx SPE APU orc evmergehi SPE APU ori evmergehilo...

Page 201: ...d evmhogsmiaa SPE APU stdcx evmhogsmian SPE APU stdu evmhogumiaa SPE APU stdux evmhogumian SPE APU stdx evmhosmf SPE APU stfd evmhosmfa SPE APU stfdu evmhosmfaaw SPE APU stfdux evmhosmfanw SPE APU stf...

Page 202: ...bfze o evmwlsmiaaw SPE APU sync Replaced with msync Replaced with msync evmwlsmianw SPE APU tlbia evmwlssiaaw SPE APU tlbie evmwlssianw SPE APU tlbivax evmwlumi SPE APU tlbre evmwlumia SPE APU tlbsx e...

Page 203: ...NOTE Some of these definitions differ slightly from those used to describe previous processors that implement the PowerPC architecture in particular with respect to dispatch issue finishing retiremen...

Page 204: ...updated the architected registers Issue The stage responsible for reading source operands from rename registers and register files This stage also assigns instructions to the proper execution unit Lat...

Page 205: ...ted in more than one stage simultaneously especially in the sense that a stage can be seen as a physical resource For example when instructions are dispatched they are assigned a place in the CQ at th...

Page 206: ...d MU execution units are also multiple stage pipelines Figure 4 1 Instruction Flow Pipeline Diagram Showing Pipeline Stages Decode Stage SU1 Maximum four instruction BU BU SU2 fetch per clock cycle Fe...

Page 207: ...ughput Instruction Cache Branch Issue Queue Decode Dispatch 2 instructions per clock cycle IQ9 IQ2 IQ1 IQ0 IQ11 IQ10 LSU 1 LSU 2 LSU 3 SU2 Signals completion queue when execution finishes CQ13 CQ1 CQ2...

Page 208: ...FB shown in Figure 4 8 Likewise on a cache miss as many as four instructions can be forwarded to the fetch unit from the line fill buffer as the cache line is passed to the instruction cache Fetch tim...

Page 209: ...rised of individual non blocking execution units implemented in parallel Each execution unit has a reservation station that must be available for an instruction issue to occur In most cases instructio...

Page 210: ...sed for SPE and floating point vector instructions Only the lower half is used by scalar instructions including embedded single precision floating point instructions The execution unit executes the in...

Page 211: ...tations The black stripe is a reminder that the instruction occupies an entry in the CQ described in Figure 4 4 Execute The operations specified by an instruction are being performed by the appropriat...

Page 212: ...the IQ during each clock cycle Two instructions per clock cycle can be dispatched to the issue queues Two instructions from the GIQ and one instruction from the BIQ can issue per clock cycle to the a...

Page 213: ...update either the LR or CTR write back their results in a similar fashion Section 4 3 1 General Instruction Flow describes this process 4 3 1 General Instruction Flow To resolve branch instructions an...

Page 214: ...1 TLB arrays miss the access proceeds to the L2 TLB arrays For L1 instruction address translation misses the L2 TLB latency is at least 5 clocks for L1 data address translation misses the L2 TLB laten...

Page 215: ...r the request for as many as four instructions to enter the IQ The cache is not blocked to internal accesses during a cache reload hits under misses The cache allows a hit under one miss and is only b...

Page 216: ...gins during the same clock cycle that the rename register is updated with the data the instruction is dependent on The CQ maintains program order after instructions are dispatched guaranteeing in orde...

Page 217: ...nd completion to one per cycle There are six basic types of instruction serialization Presync serialization Presync serialized instructions are held in the instruction queue until all prior instructio...

Page 218: ...ction In general all stores and cache operation instructions are store serialized 4 3 4 Interrupt Latency The e500v1 flushes all instructions in the completion queue when an interrupt is taken except...

Page 219: ...sactions caused by prior instructions complete entirely in its caches and externally on the bus address and data complete on the bus excluding instruction fetches No subsequent instructions and associ...

Page 220: ...echanisms However unlike msync and mbar with MO 0 subsequent instructions can complete without waiting for mbar to perform its address bus tenure This provides a faster way to order data accesses 4 4...

Page 221: ...resolve and complete until the cmp results are available add1 and add2 are dispatched to the GIQ In cycle 4 the bc resolves as correctly predicted add1 and add2 are issued to the SUs and are marked as...

Page 222: ...ermines the fetching path based on the prediction and the target address If the prediction is wrong subsequent instructions and their results are purged Instructions ahead of the predicted branch proc...

Page 223: ...oundary As shown in Figure 4 8 if instructions in a cache line are numbered 0 7 and the fetch group address maps to the nth instruction where n 0 1 2 3 or 4 instructions n n 1 n 2 n 3 are in the fetch...

Page 224: ...ction in the fetch group The presence of instructions such as isync before the branch instruction Figure 4 9 shows all possible fetch group addresses FGAs that can be associated with a branch instruct...

Page 225: ...gly taken is allocated for b2 at A for the fetch group address of A Later b1 is taken and thus mispredicted The BTB entry for address A becomes allocated for b1 replacing the prediction for b2 for the...

Page 226: ...BUCSR This following BTB operations are controlled through BUCSR BTB disabling BUCSR BPEN is used to enable or disable the BTB The BTB is enabled when the bit is set and disabled when it is cleared W...

Page 227: ...plies data to the GPRs by means of the LSU The core complex LSU is directly coupled to the data cache with a 64 bit 8 byte interface to allow efficient movement of data to and from the GPRs The LSU pr...

Page 228: ...em LSU L1 load miss queue LMQ As loads reach the LSU it tries to access the cache On a hit the cache returns the data If there is a miss the LSU allocates an LMQ entry and a DLFB entry The LSU then qu...

Page 229: ...Divide latency depends upon the operand data and ranges from 4 to 35 cycles as shown in Table 4 2 LSU data line fill buffer DLFB DLFB entries are used for loads and cacheable stores Stores are alloca...

Page 230: ...cases 35 evdivwx Both the lower and upper words match the criteria described above for the divwx 4 cycle case 4 Assuming the 4 cycle evdivwx case does not apply the lower and upper words match the cr...

Page 231: ...tage in clock cycle 10 Had divw2 been issued earlier it would have stalled in the reservation station until divw 1 vacated the second stage of the bypass path In other words the MU can hold as many as...

Page 232: ...alignment of operands in memory may affect performance of memory accesses in some cases significantly as shown in Table 4 4 Alignment of memory operands on natural boundaries guarantees the best perfo...

Page 233: ...4 3 describes branch instruction latencies Table 4 4 lists system operation instruction latencies The instructions in Table 4 4 are grouped by the serialization they require Except where otherwise no...

Page 234: ...structions if marked with a 0 cycle execution time do not have an execute stage and all refetch serialized instructions have 1 cycle between the time they are completed and the time the target sequent...

Page 235: ...nd BU 1 crandc BU 1 creqv BU 1 crnand BU 1 crnor BU 1 cror BU 1 crorc BU 1 crxor BU 1 mcrf BU 1 mcrxr BU 1 Presync postsync mfcr SU1 1 Move from mtcrf single field SU1 1 mtcrf multiple fields BU 2 Mov...

Page 236: ...SU1 or SU2 1 1 extsh SU1 or SU2 1 1 isel SU1 or SU2 1 mulhwu MU 4 1 1 3 mulhw MU 4 1 1 3 mulli MU 4 1 3 mullw o MU 4 1 1 3 nand SU1 or SU2 1 1 neg o SU1 or SU2 1 1 nor SU1 or SU2 1 1 orc SU1 or SU2 1...

Page 237: ...equent instruction can execute while CR results are generated 2 The MU provides a bypass path that allows divide instructions to perform the iterative operations necessary for division without blockin...

Page 238: ...e evstddx 3 1 Store evstdh 3 1 Store evstdhx 3 1 Store evstdw 3 1 Store evstdwx 3 1 Store evstwhe 3 1 Store evstwhex 3 1 Store evstwho 3 1 Store evstwhox 3 1 Store evstwwe 3 1 Store evstwwex 3 1 Store...

Page 239: ...resync lwbrx 3 1 lwz 3 1 lwzu 3 1 3 lwzux 3 1 3 lwzx 3 1 mbar 3 1 Store serialized msync Latency depends on bus response time Store and postsync serialized stb 3 1 Store stbu 3 1 3 Store stbux 3 1 3 S...

Page 240: ...cycles may be needed for the data to reach the cache If the cache remains busy subsequent cache operations cannot execute 2 Section 4 3 3 3 Instruction Serialization describes the different types of...

Page 241: ...tsf MU 4 1 efsctsi MU 4 1 efsctsiz MU 4 1 efsctuf MU 4 1 efsctui MU 4 1 efsctuiz MU 4 1 efsdiv MU 1 4 if either rA or rB is 0 0 29 all other cases efsmul MU 4 1 efsnabs SU1 or SU2 4 1 efsneg SU1 or SU...

Page 242: ...ther the 4 or 11 cycle evdivwx cases apply the lower and upper words match the criteria described for the divwx 4 11 or 19 cycle case 1 All other cases1 1 eveqv SU1 evextsb SU1 1 evextsh SU1 1 evfsabs...

Page 243: ...a MU 4 1 evmhesmfaaw MU 4 1 evmhesmfanw MU 4 1 evmhesmi MU 4 1 evmhesmia MU 4 1 evmhesmiaaw MU 4 1 evmhesmianw MU 4 1 evmhessf MU 4 1 evmhessfa MU 4 1 evmhessfaaw MU 4 1 evmhessfanw MU 4 1 evmhessiaaw...

Page 244: ...4 1 evmhossianw MU 4 1 evmhoumi MU 4 1 evmhoumia MU 4 1 evmhoumiaaw MU 4 1 evmhoumianw MU 4 1 evmhousiaaw MU 4 1 evmhousianw MU 4 1 evmra MU 4 1 evmwhsmf MU 4 1 evmwhsmfa MU 4 1 evmwhsmi MU 4 1 evmwhs...

Page 245: ...mwssfaa MU 4 1 evmwssfan MU 4 1 evmwumi MU 4 1 evmwumia MU 4 1 evmwumiaa MU 4 1 evmwumian MU 4 1 evnand SU1 1 evneg SU1 1 evnor SU1 1 evor SU1 1 evorc SU1 1 evrlw SU1 1 evrlwi SU1 1 evrndw SU1 1 evsel...

Page 246: ...ched at a time Schedule instructions to minimize stalls due to busy execution units Avoid scheduling high latency instructions close together Interspersing single cycle latency instructions between lo...

Page 247: ...when not all addresses are known at compile time or link time Because performance is typically not good position independent code should be avoided when possible 4 7 2 Dispatch Unit Resource Requirem...

Page 248: ...7 3 Issue Queue Resource Requirements Instructions cannot be issued unless the specified execution unit is available The following sections describe how to optimize use of the issue queues 4 7 3 1 Gen...

Page 249: ...Q0 is a mispredicted branch the entry in CQ1 should not be considered valid These and other less common conditions are described in the e500 Software Optimization Guide 4 7 4 1 Completion Groupings Th...

Page 250: ...ion at the same time as an executing divide instruction As shown in Figure 4 1 and Figure 4 1 the MU consists of a multiply subunit and a divide subunit These subunits share the same reservation stati...

Page 251: ...es cause alignment exceptions if they cross their natural alignment boundaries as show in Figure 4 9 Frequent unaligned accesses are discouraged because of the impact on performance Note the following...

Page 252: ...Pipeline As shown in Figure 4 10 the e500v1 supports as many as four outstanding load misses in the load miss queue LMQ the e500v2 LMQ supports as many as nine Table 4 10 shows a load followed by a de...

Page 253: ...ceptions as being generated by signals from internal and external peripherals instructions the internal timer facility debug events or error conditions There are three categories of interrupts describ...

Page 254: ...ordered interrupt is taken See Section 5 10 Interrupt Ordering and Masking All interrupts except the machine check interrupt are context synchronizing as defined in the instruction model chapter of th...

Page 255: ...is clear and software attempts to execute any of the SPE instructions the SPE unavailable interrupt is taken If this bit is set software can execute any SPE instructions NOTE On the e500v1 all SPFP in...

Page 256: ...ion does not support IAC3 IAC4 DAC3 and DAC4 comparisons The core complex supports instruction address compare IAC1 and IAC2 and data address compare DAC1 and DAC2 for effective addresses only Real ad...

Page 257: ...miss or data storage interrupt Interrupt vector prefix register IVPR IVPR 32 47 provides the high order 48 bits of the address of the interrupt handling routine for each interrupt type The 16 bit vec...

Page 258: ...terrupt is taken the MCSR is updated to differentiate between machine check conditions Table 5 4 lists e500 bit assignments The MCSR also indicates whether a machine check condition is recoverable ABI...

Page 259: ...ordering exception Data storage instruction storage 47 55 Reserved should be cleared 56 SPE SPE exception bit Book E allocates this bit for implementation dependent use so it may have different functi...

Page 260: ...e program interrupt is taken Execution of a defined instruction using an invalid form illegal instruction exception type program interrupt unimplemented operation exception type program interrupt or p...

Page 261: ...rupt handling routine is the address of the instruction that would have executed next had the asynchronous interrupt not occurred Synchronous Precise Caused directly by instruction execution Synchrono...

Page 262: ...s Imprecise Imprecise interrupts may indicate the address of the instruction causing the exception that generated the interrupt or some instruction after that instruction When execution or attempted e...

Page 263: ...VOR contents are indeterminate upon reset and must be initialized by system software Interrupts do not clear reservations obtained with load and reserve instructions The operating system should do so...

Page 264: ...1 SP ST 6 Cache locking SP DLK ILK ST 7 Byte ordering SP ST BO IVOR3 Instruction storage ISI Access SP 5 20 Byte ordering SP BO IVOR4 External input A MSR EE 3 5 21 IVOR5 Alignment SP ST SPE ST 5 22 I...

Page 265: ...or implementation specific ESR bits Legend xxx no brackets means ESR xxx is set xxx means ESR xxx could be set xxx yyy means either ESR xxx or ESR yyy may be set but never both xxx yyy means either ES...

Page 266: ...MCSRR0 and MCSRR1 to save the return address and the MSR in case the machine check is recoverable Return From Machine Check Interrupt instruction rfmci is implemented to support the return to the add...

Page 267: ...state immediately on detecting the machine check condition Table 5 8 e500 Machine Check Exception Sources Source Signal Additional Enable Bits Negative edge on machine check signal mcp mcp HID0 EMCP...

Page 268: ...ache errors It describes error signaling and detection and it contains information about error recoverability The L1 caches in the e500 core complex are protected by parity Parity information is writt...

Page 269: ...set For each condition the table provides comments about recoverability whether the MCAR has the address of the bad data whether the exception is precise and how far corrupted data can go into the GPR...

Page 270: ...hen the field L1CSR1 ICPI will not be set Castout or snoop push BUS_WAERR Address bus error MCSRR0 is not meaningful MCAR is set to an address on the cache line with the error The system has enough in...

Page 271: ...mplementation cannot access data in the byte order specified by the page s endian attribute Note The byte ordering exception is provided to assist implementations that cannot support dynamically switc...

Page 272: ...ss of the instruction causing the interrupt SRR1 Set to the MSR contents at the time of the interrupt ESR ST Set if the instruction causing the interrupt is a store or store class cache management ins...

Page 273: ...exists an external input exception is presented to the interrupt mechanism and MSR EE 1 The specific definition of an external input exception is implementation dependent and is typically caused by a...

Page 274: ...defines the following alignment exception conditions Execution of a dcbz references a page marked as write through or cache inhibited A load multiple word instruction lmw reads an address that is not...

Page 275: ...n an alignment interrupt occurs the processor suppresses the execution of the instruction causing the alignment exception SRR0 SRR1 MSR DEAR and ESR are updated as shown in Table 5 16 Instruction exec...

Page 276: ...nvalid form boundedly undefined results On the e500 all instructions have invalid forms cause boundedly undefined results A reserved no op instruction no operation performed is preferred There are no...

Page 277: ...ress IVPR 32 47 IVOR10 48 59 0b0000 MSR CE ME and DE are unchanged All other MSR bits are cleared ESR PIL Set if an illegal instruction exception type program interrupt otherwise cleared PPR Set if a...

Page 278: ...h TCR FPEXT specifies one of 64 bit locations of the time base used to signal a fixed interval timer exception on a transition from 0 to 1 TCR FPEXT TCR FP 000000 selects TBU 32 TCR FPEXT TCR FP 11111...

Page 279: ...Writing a 1 to this bit causes it to be cleared writing a 0 has no effect 5 7 12 Data TLB Error Interrupt A data TLB error interrupt occurs when no higher priority exception exists and the exception d...

Page 280: ...nts at the time of the interrupt MSR CE ME and DE are unchanged All other MSR bits are cleared DEAR Set to the EA of a byte that is both within the range of the bytes being accessed by the memory acce...

Page 281: ...nd MMU Background chapter of the EREF describes how these values are set as defined by the EIS Instruction execution resumes at address IVPR 32 47 IVOR14 48 59 0b0000 WD ID MD GD ED SPID0 PID0 SAS MSR...

Page 282: ...errupts are enabled DBCR0 IDM 1 and MSR DE 1 CSRR0 is set as follows For instruction address compare IAC registers data address compare DAC1R DAC1W DAC2R and DAC2W trap TRAP or branch taken BRT debug...

Page 283: ...cleared and an SPE embedded scalar double precision e500v2 only or embedded vector single precision floating point instruction is executed It is not used by the embedded scalar single precision float...

Page 284: ...ettings Instruction execution resumes at address IVPR 32 47 IVOR33 48 59 0b0000 5 7 15 3 Embedded Floating Point Round Interrupt The embedded floating point round interrupt is taken on any of the foll...

Page 285: ...errupt condition could occur with MSR EE 0 the interrupt cannot be taken until MSR EE 1 If a counter overflows while PMGC0 FCECE 0 PMLCan CE 1 and MSR EE 0 it is possible for the counter to wrap aroun...

Page 286: ...ny load bytes at the addressed location may have beenaccessed if read access to thatpage in which bytes were accessed is permitted by the access control mechanism For load multiple or load string some...

Page 287: ...hich is edge triggered All asynchronous interrupt types and some synchronous interrupt types can be masked The PowerPC architecture allows implementations to avoid situations in which an interrupt wou...

Page 288: ...synchronous interrupts as well as in the case of MSR DE any debug interrupts including synchronous and asynchronous types Branching or sequential execution to addresses not mapped by the TLB mapped wi...

Page 289: ...5 noncritical interrupts are immediately followed by the highest priority existing critical interrupt type without executing any instructions at the noncritical interrupt handler This is because noncr...

Page 290: ...ermitted setting of multiple exceptions for which the corresponding interrupt types are disabled The generation of exceptions for which the corresponding interrupt types are disabled has no effect on...

Page 291: ...truction address compare 8 ITLB miss 9 ISI 10 SPE embedded floating point APU unavailable 11 Program 12 DTLB miss 13 DSI 14 Alignment 15 Embedded floating point data interrupt 16 Embedded floating poi...

Page 292: ...d store tag when lac_clear_guarded is asserted the guarded attribute in CQ0 is cleared This process allows the completion unit to take an interrupt If a cache inhibited stwcx gets an address error the...

Page 293: ...e logic to initiate actions that cause the core complex to enter core halted state as follows Suspend instruction fetching Complete all previously fetched instructions When the instruction pipeline is...

Page 294: ...logic may similarly stop clocking to idle device level blocks tben I Asserted by the integrated device logic to enable the time base tbint O Asserted when a time base interrupt is signaled This ordin...

Page 295: ...input which suspends timer facility operations Note that tben controls the time base and decrementer in all power management states Timer operation is independent of power management except for softwa...

Page 296: ...power saving state doze nap or sleep has been previously set up by setting the appropriate HID0 bit typically at system start up time Setting MSR WE does not directly affect instruction execution but...

Page 297: ...ould typically respond to doze nap and sleep and control the core s power state through the halt halted stop stopped and tben tbint signal pairs Figure 6 2 Example Core Power Management Handshaking MS...

Page 298: ...he handler issues an rfi rfci or rfmci As a result doze nap and sleep outputs negate to the external power management logic on entry to the interrupt service routine and then return to their previous...

Page 299: ...s mispredicted branches or the number of cycles an execution unit stalls The count of such events can be used to trigger the performance monitor interrupt The performance monitor can be used to do the...

Page 300: ...ned to interrupt vector offset register 35 IVOR35 Its priority is less than the fixed interval interrupt and greater than the decrementer interrupt Software communication with the performance monitor...

Page 301: ...tor global control 0 PMGC0 Table 7 2 Performance Monitor Registers User Level Read Only Number PMR 0 4 PMR 5 9 Name Abbreviation 0 00000 00000 Performance monitor counter 0 UPMC0 1 00000 00001 Perform...

Page 302: ...t value until it is changed by software 0 The PMCs are incremented if permitted by other PM control bits 1 The PMCs are not incremented 33 PMIE Performance monitor interrupt enable 0 Performance monit...

Page 303: ...ors in the system Time base frequency is implementation dependent so software should invoke a system service program to obtain the frequency before choosing a TBSEL value 53 54 Reserved should be clea...

Page 304: ...ounter in supervisor state 0 The PMC can be incremented if enabled by other performance monitor control fields 1 The PMC cannot be incremented if MSR PR is cleared 34 FCU Freeze counter in user state...

Page 305: ...ld is multiplied by 1 PMLCbn THRESHOLD 1 001 Threshold field is multiplied by 2 PMLCbn THRESHOLD 2 010 Threshold field is multiplied by 4 PMLCbn THRESHOLD 4 011 Threshold field is multiplied by 8 PMLC...

Page 306: ...interrupt is masked for many cycles during which the counters may continue incrementing A high order bit is set normally only when the counter increments from a value below 2 147 483 648 0x8000_0000 t...

Page 307: ...s clear until after the counter leaves the overflow state msb becomes 0 or if EE remains clear until after PMLCan CE or PMGC0 PMIE cleared the exception is not signaled The following sequence is recom...

Page 308: ...s clear and freezing of the counters is not enabled PMGC0 FCECE is clear PMCn can wrap around to all zeros again without the performance monitor interrupt being taken 7 5 Event Counting This section d...

Page 309: ...nter control or by setting PMLCan FCS and PMLCan FCU for each counter control 7 6 Examples The following sections provide examples of how to use the performance monitor facility 7 6 1 Chaining Counter...

Page 310: ...l buffer DLFB load miss cycles event C0 76 and C1 76 require a threshold value A DLFB load miss cycles event is counted only when the number of cycles spent recovering from the miss is greater than th...

Page 311: ...2 for load store with update 1 32 for load or store multiple instructions Com 4 Instructions fetched Spec Fetched instructions 0 1 2 3 or 4 per cycle instructions written to the IQ Com 5 Micro ops de...

Page 312: ...Cycles MU is not empty but 0 instructions scheduled Com 24 Cycles LRU schedule stalled Spec Cycles LRU is not empty but 0 instructions scheduled Com 25 Cycles BU schedule stalled Spec Cycles BU is not...

Page 313: ...c Counts number of stalls Com 55 counts cycles stalled Com 48 Data MMU miss Spec Counts number of stalls Com 56 counts cycles stalled Com 49 Data MMU busy Spec Counts number of stalls Com 57 counts cy...

Page 314: ...ide requests Spec Master instruction side assertions of ts Com 69 BIU master data side requests Spec Master data side assertions of ts Com 70 BIU master data side castout requests Spec Includes replac...

Page 315: ...ng fetch to the critical interrupt vector exceeds the threshold See note for previous event Chaining Events3 Com 82 PMC0 overflow N A PMC0 32 transitions from 1 to 0 Com 83 PMC1 overflow N A PMC1 32 t...

Page 316: ...PowerPC e500 Core Family Reference Manual Rev 1 7 18 Freescale Semiconductor Performance Monitor...

Page 317: ...he Book E PowerPC architecture 8 2 Programming Model This section describes the registers instructions and interrupts defined by the Book E architecture to support the debug facility 8 2 1 Register Se...

Page 318: ...these registers to restore state at the end of the interrupt handler Debug interrupts do not affect the save restore registers SRR0 and SRR1 and CSRR registers are not affected by the Return from Int...

Page 319: ...1R DAC1W DAC2R and DAC2W debug events trap or branch taken debug exceptions set to the address of the instruction causing the debug interrupt For instruction complete debug exceptions set to the addre...

Page 320: ...roup is a serial protocol that specifies data flow though special registers connected between test data in TDI and test data out TDO Figure 8 1 shows the TAP registers implemented by the core complex...

Page 321: ...low the system designer to disable test functions that would impede normal operation Test reset TRST is an optional JTAG signal used in the e500 to reset the TAP controller asynchronously This signal...

Page 322: ...State Meaning Asserted Negated The contents of the selected internal instruction or data register are shifted out onto this signal Valid data appears on the falling edge of TCK Quiescent except when...

Page 323: ...Address Compare Debug Event One or more instruction address compare debug events IAC1 and IAC2 occur if they are enabled and execution is attempted of an instruction at an address that meets the crit...

Page 324: ...for detecting IAC register debug events Instruction address compare debug events can occur regardless of the values of MSR DE or DBCR0 IDM When an instruction address compare debug event occurs the c...

Page 325: ...debug events can occur on read type data accesses and whether DAC1W debug events can occur on write type data accesses DBCR0 DAC2 specifies whether DAC2R debug events can occur on read type data acces...

Page 326: ...ies the following Whether all or some of the address bits for the data access must match the contents of DAC1 or DAC2 Whether the address must be inside or outside of a range specified by DAC1 and DAC...

Page 327: ...n this case CSRR0 contains the address of the instruction following the instruction that enabled the debug interrupt The debug interrupt handler can observe DBSR IDE to determine how to interpret the...

Page 328: ...ebug event occurs when any instruction completes execution so long as MSR DE and DBCR0 ICMP are both set instruction complete debug events are enabled Note that no instruction complete debug event occ...

Page 329: ...tical interrupt vector that caused the event No instructions at the noncritical interrupt handler are executed If debug interrupts are disabled when the event occurs no interrupt is generated However...

Page 330: ...lements the e500 core for details An unconditional debug event can occur regardless of the value of MSR DE and is the only debug event that does not have a corresponding debug control register enable...

Page 331: ...Caches describes the organization of the on chip level one instruction and data caches cache coherency protocols cache control instructions and various cache operations It describes the interaction th...

Page 332: ...PowerPC e500 Core Family Reference Manual Rev 1 Part II 2 Freescale Semiconductor...

Page 333: ...r a specified amount of time has elapsed unless one of the following occurs DEC is altered by software in the interim The TB update frequency changes The DEC is typically used as a general purpose sof...

Page 334: ...mer facilities HID0 Clock source select and enable The clock source for the core timer facilities is specified by two fields in the hardware implementation dependent register 0 HID0 time base enable T...

Page 335: ...ase is static there is no counting If the time base is enabled HID0 TBEN is set the clock source is determined as follows If HID0 SEL_TBCLK 0 the timer facilities are updated every 8 CCB clocks If HID...

Page 336: ...the e500v2 this frequency is the core frequency The ATBU and ATBL registers can be read by executing an mfspr instruction but cannot be written Reading the ATB or ATBL register places the lower 32 bit...

Page 337: ...e500 supports the following APUs defined by the EIS Integer select APU Performance monitor APU Signal processing engine APU SPE APU Embedded floating point APUs Embedded vector single precision floati...

Page 338: ...e BTB provides quick access to branch targets and history bits that allow efficient branch prediction The core complex also provides support for locking and unlocking BTB entries for deterministic bra...

Page 339: ...PU The alternate time base APU defines a time base counter similar to the time base defined in PowerPC architecture It is intended to be used for measuring time in implementation defined intervals It...

Page 340: ...uble precision floating point operations use the SPEFSCR as it is described in the EREF Double precision floating point instructions affect only the low element floating point status flags and leave t...

Page 341: ...FFFF_FFFF which is approximately 1 8E 307 and the minimum positive normalized value pmin is represented by the encoding 0x0010_0000_0000_0000 approximately 2 2E 308 Biased exponent values 0 and 2047 a...

Page 342: ...iplication if Aexp Bexp 1023 2046 then overflow An underflow is said to have occurred if the numerically correct result of an instruction is such that 0 r pmin or nmin r 0 In this case r may be denorm...

Page 343: ...nmax as appropriate is stored in rD If underflow occurs 0 for rounding modes RN RZ RP or 0 for rounding mode RM is stored in rD Exceptions If the contents of rA or rB are Infinity Denorm or NaN SPEFS...

Page 344: ...a32Denorm f then SPEFSCRFINV 1 result fsign 63 0 else resultsign fsign resultexp fexp 127 1023 resultfrac ffrac 29 0 rD0 63 result The single precision floating point value in the low element of rB is...

Page 345: ...32 63 SIGN I The signed integer low element in rB is converted to a double precision floating point value using the current rounding mode and the result is placed into rD Exceptions None efdcfuf efdcf...

Page 346: ...1 else cl 0 CR4 crD 4 crD 3 undefined cl undefined undefined rA is compared against rB If rA is equal to rB the bit in the crfD is set otherwise it is cleared Comparison ignores the sign of 0 0 0 Exce...

Page 347: ...nfinities and Denorms as normalized numbers using their values of e and f directly efdcmplt efdcmplt Floating Point Double Precision Compare Less Than efdcmplt crfD rA rB al rA0 63 bl rB0 63 if al bl...

Page 348: ...sult and FG and FX are updated so the handler can perform rounding efdctsi efdctsi Convert Floating Point Double Precision to Signed Integer efdctsi rD rB rD32 63 CnvtFP64ToI32Sat rB0 63 SIGN ROUND I...

Page 349: ...D is updated with the truncated result and FG and FX are updated so the handler can perform rounding efdctuf efdctuf Convert Floating Point Double Precision to Unsigned Fraction efdctuf rD rB rD32 63...

Page 350: ...FG and FX are updated so the handler can perform rounding efdctuiz efdctuiz Convert Floating Point Double Precision to Unsigned Integer with Round toward Zero efdctuiz rD rB rD32 63 CnvtFP64ToI32Sat r...

Page 351: ...rB is 0 and the content of rA is a finite normalized non zero number SPEFSCR FDBZ is set If floating point divide by zero Exceptions are enabled an interrupt is then taken Otherwise if an overflow oc...

Page 352: ...is set an interrupt is taken and rD is not updated Otherwise if an overflow occurs SPEFSCR FOVF is set or if an underflow occurs SPEFSCR FUNF is set If either underflow or overflow exceptions are enab...

Page 353: ...for a normalized number If SPEFSCR FINVE 1 an interrupt is taken and rD is not updated efdneg efdneg Floating Point Double Precision Negate efdneg rD rA rD0 63 rA0 rA1 63 The sign bit of rA is complem...

Page 354: ...et If SPEFSCR FINVE is set an interrupt is taken and rD is not updated Otherwise if an overflow occurs SPEFSCR FOVF is set or if an underflow occurs SPEFSCR FUNF is set If either underflow or overflow...

Page 355: ...trict IEEE 754 compliance is required the program should use efdcmpeq efdtstgt efdtstgt Floating Point Double Precision Test Greater Than efdtstgt crfD rA rB al rA0 63 bl rB0 63 if al bl then cl 1 els...

Page 356: ...efined rA is compared against rB If rA is less than rB the bit in the crfD is set otherwise it is cleared Comparison ignores the sign of 0 0 0 The comparison proceeds after treating NaNs Infinities an...

Page 357: ...rB is converted to a single precision floating point value using the current rounding mode and the result is placed into the low element of rD Exceptions If the rB value is Infinity Denorm or NaN SPEF...

Page 358: ...malized positive number The encoding for double precision is 0x0010_0000_0000_0000 nmin denotes the minimum normalized negative number The encoding for double precision is0x8010_0000_0000_0000 10 4 5...

Page 359: ...p fpsign 0b11111110 231 else fpexp fpexp 1 fpfrac v1 23 else fpfrac v1 23 else if SPEFSCRFRMC 0b10 0b10 then infinity modes implementation dependent return fp Round a result Round64 fp guard sticky FP...

Page 360: ...f fpexp 0 fpfrac 0 then return 0x00000000 all zero values if fractional I then convert to integer max_exp 1054 shift 1054 fpexp if signed SIGN then if fpexp 1054 fpfrac 0 fpsign 1 then max_exp max_exp...

Page 361: ...uration Convert from integer fractional to 64 bit floating point signed SIGN or UNSIGN fractional F fractional or I integer CnvtI32ToFP64Sat v signed fractional FP64format result resultsign 0 if v 0 t...

Page 362: ...PowerPC e500 Core Family Reference Manual Rev 1 10 26 Freescale Semiconductor Auxiliary Processing Units APUs...

Page 363: ...hat can access system memory maintain their own caches and function as bus masters requiring cache coherency 11 1 Overview The core complex L1 cache implementation has the following characteristics Se...

Page 364: ...ith respect to the data cache Both instruction and data cache lines are filled in a single cycle 32 byte write from line fill buffers as described in Section 11 1 1 1 Load Store Unit LSU and Section 1...

Page 365: ...ignment to and from the data cache provides sequencing for load store multiple operations and interfaces with the core interface unit Write operations to the data cache can be performed on a byte half...

Page 366: ...v2 and the three entry data line fill buffer DLFB five entry in the e500v2 see Section 4 4 2 1 Load Store Unit Queueing Structures The LSU then queues a bus transaction to read the line If a subsequen...

Page 367: ...outs and one that can be used for either 11 1 1 2 Instruction Unit The instruction unit interfaces with the L1 instruction cache and the core interface unit When instructions miss in the instruction c...

Page 368: ...rovide the index to select a cache set The tags consist of physical address bits PA 0 19 Address translation occurs in parallel with set selection from PA 20 26 Lower address bits PA 27 31 locate a by...

Page 369: ...t and PA 27 28 selects an instruction within a block The tags consist of physical address bits PA 0 19 Address translation occurs in parallel with set selection from PA 20 26 The instruction cache can...

Page 370: ...L1 caches whenever one of the following occurs A store instruction or dcbz or dcba modifies the data cache A line fill occurs into the instruction or data cache L1 cache parity is checked whenever A...

Page 371: ...L1CSR1 ICPI is set Similarly for the data cache L1CSR0 CPE must be set if L1CSR0 CPI is set If the programmer attempts to set L1CSR0 CPI using mtspr without setting L1CSR0 CPE then L1CSR0 CPI will no...

Page 372: ...respect to main memory It does not reside in any other coherent caches 100 Exclusive E The line is present in the cache and this cache has exclusive ownership of the line It is not present in any oth...

Page 373: ...ts only invalid and valid state Table 11 3 describes how execution of instruction cache control instructions affect L1 instruction cache coherency states dcbtstls CT 1 00x Any I dcbz 00x Any M icblc C...

Page 374: ...snooped by other bus masters To determine the action to take due to a snoop the cache coherency protocol uses transfer type ttx encodings which are transmitted on the CCB with the address See Section...

Page 375: ...gh and the other mapped as write back that is non write through In this case the cache line remains in its current state the store data is written into the data cache and the store goes to the CCB as...

Page 376: ...an be recognized when a guarded load is in progress so the above precautions do not apply 11 3 5 Load Store Operations Load and store operations are assumed to be weakly ordered on the core complex Th...

Page 377: ...they do not store to overlapping bytes of data Note that although memory accesses that miss in the L1 cache are forwarded onto the core interface unit for future arbitration onto the CCB all potential...

Page 378: ...on specific information The remainder of this section describes how the cache control instructions and the L1CSRn bits are used to control the L1 cache 11 4 1 Cache Control Instructions The following...

Page 379: ...r L1CSR0 CUL Acronyms are used to signify the following interrupts DTLB data TLB interrupt ALI alignment interrupt DSI data storage interrupt icbt Instruction Cache Touch no op x icbtls Instruction Ca...

Page 380: ...nored and the corresponding cache is not accessed The default power up state of L1CSR0 CE and L1CSR1 ICE is zero caches disabled When the data cache is disabled snooping of lines in the cache is not p...

Page 381: ...e that invalidating the caches resets all cache status bits including lock bits Also note that with dcbi the e500 core invalidates the cache block without pushing it out to memory See Section 3 3 1 8...

Page 382: ...ll for a new address in a completely locked cache set will not be put into the cache It is however loaded into a DWB and creates the appropriate normal burst write transfer The cache locking DSI handl...

Page 383: ...owing cache instructions are treated as stores and may cause the invalidation and unlocking of a cache line in another processor in a multiprocessor system dcba dcbz In implementations with an L2 cach...

Page 384: ...ion then execute dcbf instructions to that region Note that a 48 Kbyte region must be used to ensure that the PLRU algorithm flushes all of the cache entries 12 x 128 sets x 32 bits 48 Kbytes Perform...

Page 385: ...not loaded into the data cache If the data is modified it is loaded into a DWB and creates the appropriate normal burst write transfer Each of the eight ways of each set in the instruction cache can b...

Page 386: ...not cause a fill Also cache operations such as dcbi and dcbf that miss in the cache do not cause a fill 11 6 1 4 Store Miss Merging When a caching allowed store misses in the data cache an entry is a...

Page 387: ...L1 data cache function similarly to L1 instruction cache misses They cause a new line to be allocated on a PLRU basis provided the cache is not completely locked or disabled Note that modified data i...

Page 388: ...set are updated using the rules specified in Table 11 9 Note that only three PLRU bits are updated for any access Table 11 9 PLRU Bit Update Rules Current Access New State of the PLRU Bits B0 B1 B2 B3...

Page 389: ...B the core complex provides an address lock attribute CL on the bus which can be used in conjunction with the transfer type ttx encodings to identify which addresses to lock or unlock When the core co...

Page 390: ...2 cache may also use other bus transactions to cause locks to be cleared such as bus transactions as a result of dcbf identified on the bus as an address only FLUSH or as an L1 push due to dcbf 11 7 2...

Page 391: ...l 2 L2 MMU The L1 MMUs are completely invisible with respect to the architecture The programming model for implementing translation lookaside buffers TLBs provided in Book E and the Freescale Book E s...

Page 392: ...es resident in L2 MMU completely maintained by the hardware Automatically performs invalidations to maintain consistency with L2 TLBs The level 2 MMU has the following features A 16 entry fully associ...

Page 393: ...y instruction 12 4 1 12 18 tlbwe TLB Write Entry instruction 12 4 2 12 19 tlbsx rA rB preferred form is tlbsx 0 rB TLB Search for entry instruction 12 4 3 12 19 tlbivax rA rB TLB Invalidate entries in...

Page 394: ...cant 12 bits always index within the page and are untranslated The appropriate L1 MMU instruction or data is checked for a matching address translation first If it misses the request for translation i...

Page 395: ...respectively The e500 constructs three virtual addresses for each access The core complex implements three process ID PID registers PID0 PID2 as SPRs shown in Section 2 12 1 Process ID Registers PID0...

Page 396: ...ddress spaces 12 2 2 Variable Sized Pages There are two kinds of TLBs on the e500 core complex as follows TLBs that translate addresses for 4 Kbyte pages only These TLBs are set associative based on t...

Page 397: ...ess A hit to multiple matching TLB entries is considered a programming error If this occurs the TLB generates an invalid address and TLB entries may be corrupted an exception is not reported Figure 12...

Page 398: ...ative TLB0 in the e500v2 Figure 12 4 Two Level MMU Structure Additionally Figure 12 4 shows that when the L2 MMU is checked for a TLB entry both TLB1 and TLB0 are checked in parallel It also identifie...

Page 399: ...accesses both the L1TLB4K and the L1VSP TLBs in the instruction MMU are searched in parallel for the matching TLB entry Similarly for data accesses both the L1TLB4K and the L1VSP TLBs in the data MMU...

Page 400: ...U replacement algorithm The LRU bits are updated each time a TLB entry is accessed for translation However there are other speculative accesses performed to the L1 MMUs that cause the LRU bits to be u...

Page 401: ...associative array that supports nine e500v1 or eleven e500v2 page sizes TLB0 a 256 entry 2 way e500v1 or 512 entry 4 way e500 v2 set associative array that supports only 4 Kbyte page sizes The two L2...

Page 402: ...cated internal case by an external tlbivax instruction or by a flash invalidate initiated by writing to the MMUCSR0 The IPROT bit can be used to protect critical code and data such as interrupt vector...

Page 403: ...implemented completely by the system software Thus when an entry in TLB1 is to be replaced the software selects which entry to replace and writes the entry number to the MAS0 ESEL field before execut...

Page 404: ...re automatically loads the current value of TLB0 NV1 into MAS0 ESEL and the complement of TLB0 NV into MAS0 NVlsb This sets up MAS0 such that if those values are not overwritten the alternate way will...

Page 405: ...reloaded using entries from their level 2 array equivalent For example if the L1 data MMU misses but there is a hit for one of the three virtual addresses in TLB1 the matching entry is automatically l...

Page 406: ...come inaccessible due to the snooping activity caused by the TLBINV 12 3 5 The G Bit of WIMGE The G bit provides protection from bus accesses due to speculative and faultable instruction execution A s...

Page 407: ...ad Entry tlbre instruction and data is written to the TLBs from the MAS registers with a TLB Write Entry tlbwe instruction Table 12 4 TLB Entry Bit Definitions for e500 Field Comments V Valid bit for...

Page 408: ...MAS3 and MAS7 if HID0 EN_MAS7_UPDATE 1 result Note that architecturally if the instruction specifies a TLB entry that is not found the results placed in MAS0 MAS3 and optionally MAS7 are undefined Ho...

Page 409: ...and then executing the tlbwe instruction To write an entry into TLB1 MAS0 TLBSEL must 01 and MAS0 ESEL must point to the desired entry When the tlbwe instruction is executed the TLB entry information...

Page 410: ...is especially useful for finding the TLB entry that caused a DSI or ISI exception In this case at most three tlbsx instructions are required one for each of the current PID values Note that TID value...

Page 411: ...he core complex always snoops TLB invalidate transactions from other CCB bus masters if any and invalidates matching TLB entries accordingly Note that entries in TLB1 can be protected from invalidatio...

Page 412: ...sync instruction has pending memory accesses that were issued before any previous tlbivax instructions were completed This instruction effectively synchronizes the invalidation of TLB entries tlbsync...

Page 413: ...ore information on some of the actions taken by Freescale Book E devices on MMU exceptions The following subsections provide supplementary information that applies for the e500 12 5 1 Automatic Update...

Page 414: ...E devices and for the e500 is that the e500 only uses MAS6 SPID0 and the e500 does not implement MAS5 Note that for a permissions violation case software must explicitly load a value into MAS6 SPID0 t...

Page 415: ...ces to other sections that have more detailed bit descriptions for the e500 registers related to the MMU Also the EREF lists the Freescale Book E definitions for these registers Table 12 6 TLB1 Entry...

Page 416: ...ts 46 47 that identifies which of the indexed entries is to be referenced by the TLB operation ESEL selects the way For TLB1 ESEL selects one of the 16 entries in the array Figure 12 11 describes the...

Page 417: ...s field is updated based on the calculated next victim value for TLB0 based on the round robin replacement algorithm described in Section 12 3 2 2 Replacement Algorithms for L2 MMU Note that for the e...

Page 418: ...Mbyte 1010 1 Gbyte 1011 4 Gbyte 56 63 Reserved should be cleared SPR 626 Access Supervisor only 32 51 52 56 57 58 59 60 61 62 63 R EPN X0 X1 W I M G E W Reset All zeros Figure 12 13 MAS Register 2 MA...

Page 419: ...ian which differs from the modified little endian byte ordering model optionally available in previous devices that implement the original PowerPC architecture 0 The page is accessed in big endian byt...

Page 420: ...e current PID registers should be used to load the MAS1 TID field on a TLB miss exception The e500 implementation defines this field as follows 00 PID0 01 PID1 10 PID2 11 TIDZ 0x00 all zeros 48 51 Res...

Page 421: ...0 EN_MAS7_UPDATE Figure 12 17 shows the format of the MAS7 register The MAS7 fields are described in Table 12 14 SPR 630 Access Supervisor only 32 39 40 47 48 62 63 R SPID0 SAS W Reset All zeros Figur...

Page 422: ...TLBSELD 0 TLB0 NV else undefined if TLBSEL 0 TLB0 NV else undefined if TLBSELD 0 TLB0 NV else undefined if TLBSEL 0 TLB0 NV else undefined V 1 1 0 V array IPROT 0 Matched IPROT if TLB1 hit else 0 0 I...

Page 423: ...defined as follows High speed on chip local bus interface 32 bit address bus Address protocol with address pipelining and retry copyback derived from bus used by previous generations of PowerPC proces...

Page 424: ...inhibit Normally reflected from the I bit of the WIMGE bits regardless of whether the cache is enabled For burst writes and address only transactions ci is always negated cl O Cache lock Indicates L2...

Page 425: ...500 clock Refer to Chapter 8 Debug Support ckstp_out O Checkstop interrupt Assertion of this signal by the e500 core is used by system to generate a chip wide hard stop and to signal an external CKSTP...

Page 426: ...then halt so the interrupt can be serviced wrs 0 1 O Watchdog timer reset status These two bits are set to one of three values when a reset is caused by the watchdog timer These bits are undefined at...

Page 427: ...after the core complex has entered halted state otherwise the negation may not be recognized stop I Asserted by system logic to request that the core complex go from the halted state into the power d...

Page 428: ...ctions and associated memory transactions are initiated until such completion occurs Execution of msync also generates a SYNC command on the bus if HID1 ABE is set through the tt 0 4 signals which als...

Page 429: ...lex in certain clock modes to process a snoop transaction Note that address streaming as defined here differs from address pipelining which is the issue of multiple address tenures independent of whet...

Page 430: ...ck the specified address from its cache This transaction is always performed as non global because it is specifically targeted at an L2 cache An L2 cache may also use other bus transactions to cause l...

Page 431: ...cx behavior defined by the PowerPC architecture such use would have to be carefully controlled by the system 13 7 Remote Atomic Status Monitoring For system convenience the core complex provides a sys...

Page 432: ...use of the machine check This is the only instance where RFXE should be set except for the case for the e500v1 described in the HID1 RFXE bit description of Section 2 10 2 Hardware Implementation Depe...

Page 433: ...how the retry strategy can affect performance Load and reserve and store conditional instructions depend on the coherence mechanism of the system Stores to a given location are coherent if they are se...

Page 434: ...show how the lwarx and stwcx instructions can be used to implement various synchronization primitives The sequences used to emulate the various primitives consist primarily of a loop using lwarx and s...

Page 435: ...s of the word to be incremented is in GPR3 the increment is in GPR4 and the old value is returned in GPR5 loop lwarx r5 0 r3 load and reserve add r0 r4 r5 increment word stwcx r0 0 r3 store new value...

Page 436: ...arison In this example it is assumed that the address of the word to be tested is in GPR3 the comparand is in GPR4 and the old value is returned there and the new value is in GPR5 loop lwarx r6 0 r3 l...

Page 437: ...e of Section A 1 1 Synchronization Primitives thereby atomically loading the old value of the lock writing to the lock the new value 1 given in GPR4 returning the old value in GPR5 not used below and...

Page 438: ...ement pointer is at offset 0 from the start of the element It is also assumed that the next element pointer of each list element is in a reservation granule separate from that of the next element poin...

Page 439: ...ocessor is implementation dependent see Section 3 3 1 7 Atomic Update Primitives Using lwarx and stwcx In some implementations performance may be improved by minimizing looping on a lwarx instruction...

Page 440: ...PowerPC e500 Core Family Reference Manual Rev 1 A 8 Freescale Semiconductor Programming Examples...

Page 441: ...64 Bit Specific Book E Instructions A subset of Book E instructions are restricted to 64 bit Book E processing A 32 bit Book E implementation need not implement any of the following instructions Like...

Page 442: ...eed to be calculated and presented to main memory Given that only branch and data memory access instructions not included in Section B 1 64 Bit Specific Book E Instructions are defined to prepend 32 z...

Page 443: ...produce the full 64 bit address Book E also provides a complete set of branch instructions that perform a modulo 232 on the computed branch target effective address and then prepend 32 zeros to produc...

Page 444: ...PowerPC e500 Core Family Reference Manual Rev 1 B 4 Freescale Semiconductor Guidelines for 32 Bit Book E...

Page 445: ...mer to program using more intuitive mnemonics and symbols than the instructions and syntax defined by the instruction set architecture For example to code the conditional call branch to an absolute ta...

Page 446: ...be difficult to understand Simplified mnemonics are provided for the following operations Extract Select a field of n bits starting at bit position b in the source register left or right justify this...

Page 447: ...left 8 bits slwi rA rA 8 equivalent to rlwinm rA rA 8 0 23 4 Clear the high order 16 bits of rS and place the result into rA clrlwi rA rS 16 equivalent to rlwinm rA rS 0 16 31 Table C 3 Word Rotate an...

Page 448: ...s for BO and BI For example bc 16 0 target is a conditional branch that as a BO value of 16 0b1_0000 indicates decrements the CTR then branches if the decremented CTR is not zero The operation specifi...

Page 449: ...Mnemonics The following key points are helpful in understanding how to use simplified branch mnemonics All simplified branch mnemonics eliminate the BO operand so if any operand is present in a branc...

Page 450: ...of the Instruction Encoding Table C 5 BO Bit Encodings BO Bit Description 0 If set ignore the CR bit comparison 1 If set the CR bit comparison is against true if not set the CR bit comparison is agai...

Page 451: ...ds coding the suffix causes the bit to be set and coding the suffix causes the bit to be cleared For branches to an address in the LR or CTR bclr l or bcctr l coding the suffix causes the y bit to be...

Page 452: ...used to replace the decimal operand as shown in the example in Section C 4 Branch Instruction Simplified Mnemonics where bdnzt 4 cr5 eq target could be used instead of bdnzt 22 target This is describe...

Page 453: ...Compare Word Simplified Mnemonics move to CR instructions and others can also modify CR fields so CR0 and CR1 may hold values that do not adhere to the meanings described in Table C 7 CR logical instr...

Page 454: ...t 4 cr2 lt 4 cr3 lt 4 cr4 lt 4 cr5 lt 4 cr6 lt 4 cr7 lt 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 000 001 010 011 100 101 110 111 00 Less than LT For integer compare instructions rA SIMM or rB sign...

Page 455: ...cr4 100 48 51 cr5 101 52 55 cr6 110 56 59 cr7 111 60 63 Table C 10 Branch Simplified Mnemonics Branch Semantics LR Update Not Enabled LR Update Enabled bc bca bclr bcctr bcl bcla bclrl bcctrl Branch...

Page 456: ...ror Subsequent examples test conditions 2 Same as 1 but branch only if CTR is nonzero and equal condition in CR0 bdnzt eq target equivalent to bc 8 2 target Other equivalents include bdnzt 2 target or...

Page 457: ...ndition false bc 0 BI target bdnzf BI target bca 0 BI target bdnzfa BI target Decrement CTR branch if CTR 0 bc 18 0 target bdz target2 bca 18 0 target bdza target2 Decrement CTR branch if CTR 0 and co...

Page 458: ...CTR 0 and condition true bcl 8 0 target bdnztl BI target bcla 8 BI target bdnztla BI target Decrement CTR branch if CTR 0 and condition false bcl 0 BI target bdnzfl BI target bcla 0 BI target bdnzfla...

Page 459: ...R fields the test bit falls so the BI operand is replaced by a crS operand The standard codes shown in Table C 16 are used for the most common combinations of branch conditions Note that for ease of p...

Page 460: ...crS 2 target_addr 2 BI can be a numeric value or an expression as shown in Table C 9 Branch Conditional to Link Register bclr bclrl BO BI bxlr bxlrl crS Branch Conditional to Count Register bcctr bcct...

Page 461: ...c bca Simplified Mnemonic Branch if less than bc 12 BI 1 target 1 The value in the BI operand selects CRn 0 the LT bit blt crS target bca 12 BI1 target blta crS target Branch if less than or equal bc...

Page 462: ...not equal bclr 4 BI3 target bnelr crS target bcctr 4 BI3 target bnectr crS target Branch if summary overflow bclr 12 BI 4 target 4 The value in the BI operand selects CRn 3 the SO bit bsolr crS targe...

Page 463: ...n 1 the GT bit blelrl crS target bcctrl 4 BI2 target blectrl crS target Branch if not greater than bnglrl crS target bngctrl crS target Branch if equal bclrl 12 BI 3 target 3 The value in the BI opera...

Page 464: ...as unsigned 32 bit integers and place result in CR0 cmplw rA rB equivalent to cmpl 0 0 rA rB C 6 Condition Register Logical Simplified Mnemonics The CR logical instructions shown in Table C 24 can be...

Page 465: ...dopted for the most common combinations of trap conditions Table C 25 Standard Codes for Trap Instructions Code Description TO Encoding U 1 1 The symbol U indicates an unsigned less than evaluation is...

Page 466: ...ctions evaluate a trap condition as follows The contents of rA are compared with either the sign extended SIMM field or the contents of rB depending on the trap instruction Table C 26 Trap Simplified...

Page 467: ...destination GPR operand rS or rD Following are examples using the SPR simplified mnemonics 1 Copy the contents of rS to the XER mtxer rS equivalent to mtspr 1 rS 2 Copy the contents of the LR to rS m...

Page 468: ...dis instructions can be used to load an immediate value into a register Additional mnemonics are provided to convey the idea that no addition is being performed but that data is being moved from the i...

Page 469: ...g instruction copies the contents of rS into rA This mnemonic can be coded with a dot suffix to cause the Rc bit to be set in the underlying instruction mr rA rS equivalent to or rA rS rS C 9 5 Comple...

Page 470: ...ent to isel rD rA rB 2 C 10 2 SPE Mnemonics The following mnemonic handles moving of the full 64 bit SPE GPR Vector Move evmr rD rA equivalent to evor rD rA rA The following mnemonic performs a comple...

Page 471: ...crement CTR branch if CTR 0 bclrl with LR Update bdnzt BI target bc 8 BI target Decrement CTR branch if CTR 0 and condition true bc without LR update bdnzta BI target bca 8 BI target Decrement CTR bra...

Page 472: ...10 BI target Decrement CTR branch if CTR 0 and condition true bcl with LR update bdztla BI target bcla 10 BI target Decrement CTR branch if CTR 0 and condition true bcla with LR update bdztlrl BI bclr...

Page 473: ...updating bgela crS target bcla 4 BI4 target Branch if greater than or equal bcla with comparison conditions and LR updating bgelr crS target bclr 4 BI4 target Branch if greater than or equal bclr with...

Page 474: ...blta crS target bca 12 BI4 target Branch if less than bca without comparison conditions or LR updating bltctr crS target bcctr 12 BI4 target Branch if less than bcctr without comparison conditions an...

Page 475: ...t greater than bclr without comparison conditions and LR updating bnglrl crS target bclrl 4 BI5 target Branch if not greater than bclrl with comparison conditions and LR update bnl crS target bc 4 BI4...

Page 476: ...target Branch if not unordered bcctrl with comparison conditions and LR update bnul crS target bcl 4 BI6 target Branch if not unordered bcl with comparison conditions and LR updating bnula crS target...

Page 477: ...crS target bcctrl 12 BI6 target Branch if unordered bcctrl with comparison conditions and LR update bunl crS target bcl 12 BI6 target Branch if unordered bcl with comparison conditions and LR updating...

Page 478: ...crf 0xFF rS Move to Condition Register mtspr rS mfspr SPRN rS Move to SPR see Section C 8 Simplified Mnemonics for Accessing SPRs nop ori 0 0 0 No op not rA rS nor rA rS rS NOT not rA rS nor rA rS rS...

Page 479: ...twi 5 rA SIMM Trap immediate if logically not less than twlt rA SIMM tw 16 rA SIMM Trap if less than twlti rA SIMM twi 16 rA SIMM Trap immediate if less than twne rA SIMM tw 24 rA SIMM Trap if not equ...

Page 480: ...PowerPC e500 Core Family Reference Manual Rev 1 C 36 Freescale Semiconductor Simplified Mnemonics for PowerPC Instructions...

Page 481: ...1 1 1 1 1 rD rA rB 0 1 0 0 0 0 1 0 1 0 0 X add add 0 1 1 1 1 1 rD rA rB 0 1 0 0 0 0 1 0 1 0 1 X add addc 0 1 1 1 1 1 rD rA rB 0 0 0 0 0 0 1 0 1 0 0 X addc addc 0 1 1 1 1 1 rD rA rB 0 0 0 0 0 0 1 0 1 0...

Page 482: ...0 0 0 1 0 0 1 1 0 0 X bblels bc 0 1 0 0 0 0 BO BI BD 0 0 B bc bca 0 1 0 0 0 0 BO BI BD 1 0 B bca bcctr 0 1 0 0 1 1 BO BI 1 0 0 0 0 1 0 0 0 0 0 XL bcctr bcctrl 0 1 0 0 1 1 BO BI 1 0 0 0 0 1 0 0 0 0 1 X...

Page 483: ...uivalent to bca 2 BI target bdzfa bdzfl bdzfl BI target equivalent to bcl 2 BI target bdzfl bdzfla bdzfla BI target equivalent to bcla 2 BI target bdzfla bdzflr bdzflr BI equivalent to bclr 2 BI bdzfl...

Page 484: ...cctrl 4 BI3 target bgectrl bgel bgel crS target equivalent to bcl 4 BI3 target bgel bgela bgela crS target equivalent to bcla 4 BI3 target bgela bgelr bgelr crS target equivalent to bclr 4 BI3 target...

Page 485: ...t to bc 4 BI3 target bne bnea bnea crS target equivalent to bca 4 BI3 target bnea bnectr bnectr crS target equivalent to bcctr 4 BI3 target bnectr bnectrl bnectrl crS target equivalent to bcctrl 4 BI3...

Page 486: ...rget equivalent to bca 4 BI5 target bnua bnuctr bnuctr crS target equivalent to bcctr 4 BI5 target bnuctr bnuctrl bnuctrl crS target equivalent to bcctrl 4 BI5 target bnuctrl bnul bnul crS target equi...

Page 487: ...rA rS n n 32 equivalent to rlwinm rA rS 0 n 31 clrlwi clrrwi clrrwi rA rS n n 32 equivalent to rlwinm rA rS 0 0 31 n clrrwi cmp 0 1 1 1 1 1 crfD L rA rB 0 0 0 0 0 0 0 0 0 0 X cmp cmpi 0 0 1 0 1 1 crf...

Page 488: ...1 1 0 1 1 0 X dcbz divw 0 1 1 1 1 1 rD rA rB 0 1 1 1 1 0 1 0 1 1 0 X divw divw 0 1 1 1 1 1 rD rA rB 0 1 1 1 1 0 1 0 1 1 1 X divw divwo 0 1 1 1 1 1 rD rA rB 1 1 1 1 1 0 1 0 1 1 0 X divwo divwo 0 1 1 1...

Page 489: ...fD rA rB 0 1 0 1 1 1 1 1 1 0 1 EFX efdtstlt efsabs 0 0 0 1 0 0 rD rA 0 1 0 1 1 0 0 0 1 0 0 EFX efsabs efsadd 0 0 0 1 0 0 rD rA rB 0 1 0 1 1 0 0 0 0 0 0 EFX efsadd efscfd 0 0 0 1 0 0 rD 0 0 0 0 0 rB 0...

Page 490: ...A rB 0 1 0 0 0 0 0 0 0 0 0 EVX evaddw evand 0 0 0 1 0 0 rD rA rB 0 1 0 0 0 0 1 0 0 0 1 EVX evand evandc 0 0 0 1 0 0 rD rA rB 0 1 0 0 0 0 1 0 0 1 0 EVX evandc evcmpeq 0 0 0 1 0 0 crfD rA rB 0 1 0 0 0 1...

Page 491: ...g evfssub 0 0 0 1 0 0 rD rA rB 0 1 0 1 0 0 0 0 0 0 1 EVX evfssub evfststeq 0 0 0 1 0 0 crfD rA rB 0 1 0 1 0 0 1 1 1 1 0 EVX evfststeq evfststgt 0 0 0 1 0 0 crfD rA rB 0 1 0 1 0 0 1 1 1 0 0 EVX evfstst...

Page 492: ...1 0 0 1 0 1 0 0 1 EVX evmhegsmiaa evmhegsmian 0 0 0 1 0 0 rD rA rB 1 0 1 1 0 1 0 1 0 0 1 EVX evmhegsmian evmhegumiaa 0 0 0 1 0 0 rD rA rB 1 0 1 0 0 1 0 1 0 0 0 EVX evmhegumiaa evmhegumian 0 0 0 1 0 0...

Page 493: ...0 0 rD rA rB 1 0 1 1 0 0 0 1 1 1 1 EVX evmhosmfanw evmhosmi 0 0 0 1 0 0 rD rA rB 1 0 0 0 0 0 0 1 1 0 1 EVX evmhosmi evmhosmia 0 0 0 1 0 0 rD rA rB 1 0 0 0 0 1 0 1 1 0 1 EVX evmhosmia evmhosmiaaw 0 0...

Page 494: ...rD rA rB 1 0 1 0 1 0 0 0 0 0 0 EVX evmwlusiaaw evmwlusianw 0 0 0 1 0 0 rD rA rB 1 0 1 1 1 0 0 0 0 0 0 EVX evmwlusianw evmwsmf 0 0 0 1 0 0 rD rA rB 1 0 0 0 1 0 1 1 0 1 1 EVX evmwsmf evmwsmfa 0 0 0 1 0...

Page 495: ...wiu evsrws 0 0 0 1 0 0 rD rA rB 0 1 0 0 0 1 0 0 0 0 1 EVX evsrws evsrwu 0 0 0 1 0 0 rD rA rB 0 1 0 0 0 1 0 0 0 0 0 EVX evsrwu evstdd 0 0 0 1 0 0 rD rA UIMM 6 0 1 1 0 0 1 0 0 0 0 1 EVX evstdd evstddx 0...

Page 496: ...1 0 0 1 1 0 1 0 1 X extsh icbi 0 1 1 1 1 1 rA rB 1 1 1 1 0 1 0 1 1 0 X icbi icblc 0 1 1 1 1 1 CT rA rB 0 0 1 1 1 0 0 1 1 0 0 X icblc icbt 0 1 1 1 1 1 CT rA rB 0 0 0 0 0 1 0 1 1 0 X icbt icbtls 0 1 1...

Page 497: ...0 0 0 0 0 0 0 0 0 0 XL mcrf mcrxr 0 1 1 1 1 1 crfD 1 0 0 0 0 0 0 0 0 0 X mcrxr mfcr 0 1 1 1 1 1 rD 0 0 0 0 0 1 0 0 1 1 X mfcr mfcr mtcr rS equivalent to mtcrf 0xFF rS mfcr mfmsr 0 1 1 1 1 1 rD 0 0 0...

Page 498: ...0 0 1 X nego nop nop equivalent to ori 0 0 0 nop nor 0 1 1 1 1 1 rS rA rB 0 0 0 1 1 1 1 1 0 0 0 X nor nor 0 1 1 1 1 1 rS rA rB 0 0 0 1 1 1 1 1 0 0 1 X nor not not rA rS equivalent to nor rA rS rS not...

Page 499: ...m rA rS 32 n n 31 srwi stb 1 0 0 1 1 0 rS rA D D stb stbu 1 0 0 1 1 1 rS rA D D stbu stbux 0 1 1 1 1 1 rS rA rB 0 0 1 1 1 1 0 1 1 1 0 X stbux stbx 0 1 1 1 1 1 rS rA rB 0 0 1 1 0 1 0 1 1 1 0 X stbx sth...

Page 500: ...subfo 0 1 1 1 1 1 rD rA rB 1 0 0 0 1 0 1 0 0 0 1 X subfo subfze 0 1 1 1 1 1 rD rA 0 0 1 1 0 0 1 0 0 0 0 X subfze subfze 0 1 1 1 1 1 rD rA 0 0 1 1 0 0 1 0 0 0 1 X subfze subfzeo 0 1 1 1 1 1 rD rA 1 0 1...

Page 501: ...ent to twi 6 rA SIMM twlngi twlnl twlnl rA SIMM equivalent to tw 5 rA SIMM twlnl twlnli twlnli rA SIMM equivalent to twi 5 rA SIMM twlnli twlt twlt rA SIMM equivalent to tw 16 rA SIMM twlt twlti twlti...

Page 502: ...0 1 0 1 1 0 0 0 0 0 0 EFX efsadd efscfsf 04 rD rB 0 1 0 1 1 0 1 0 0 1 1 EFX efscfsf efscfsi 04 rD rB 0 1 0 1 1 0 1 0 0 0 1 EFX efscfsi efscfuf 04 rD rB 0 1 0 1 1 0 1 0 0 1 0 EFX efscfuf efscfui 04 rD...

Page 503: ...vcntlsw 04 rD rA 0 1 0 0 0 0 0 1 1 1 0 EVX evcntlsw evcntlzw 04 rD rA 0 1 0 0 0 0 0 1 1 0 1 EVX evcntlzw evdivws 04 rD rA rB 1 0 0 1 1 0 0 0 1 1 0 EVX evdivws evdivwu 04 rD rA rB 1 0 0 1 1 0 0 0 1 1 1...

Page 504: ...evldh 04 rD rA UIMM 1 0 1 1 0 0 0 0 0 1 0 1 EVX evldh evldhx 04 rD rA rB 0 1 1 0 0 0 0 0 1 0 0 EVX evldhx evldw 04 rD rA UIMM 1 0 1 1 0 0 0 0 0 0 1 1 EVX evldw evldwx 04 rD rA rB 0 1 1 0 0 0 0 0 0 1...

Page 505: ...B 1 0 1 0 0 0 0 1 0 1 1 EVX evmhesmfaaw evmhesmfanw 04 rD rA rB 1 0 1 1 0 0 0 1 0 1 1 EVX evmhesmfanw evmhesmi 04 rD rA rB 1 0 0 0 0 0 0 1 0 0 1 EVX evmhesmi evmhesmia 04 rD rA rB 1 0 0 0 0 1 0 1 0 0...

Page 506: ...rD rA rB 1 0 0 0 0 1 0 0 1 1 1 EVX evmhossfa evmhossfaaw 04 rD rA rB 1 0 1 0 0 0 0 0 1 1 1 EVX evmhossfaaw evmhossfanw 04 rD rA rB 1 0 1 1 0 0 0 0 1 1 1 EVX evmhossfanw evmhossiaaw 04 rD rA rB 1 0 1 0...

Page 507: ...0 1 EVX evmwsmi evmwsmia 04 rD rA rB 1 0 0 0 1 1 1 1 0 0 1 EVX evmwsmia evmwsmiaa 04 rD rA rB 1 0 1 0 1 0 1 1 0 0 1 EVX evmwsmiaa evmwsmian 04 rD rA rB 1 0 1 1 1 0 1 1 0 0 1 EVX evmwsmian evmwssf 04 r...

Page 508: ...B 0 1 1 0 0 1 0 0 0 1 0 EVX evstdwx evstwhe 04 rS rA UIMM 3 0 1 1 0 0 1 1 0 0 0 1 EVX evstwhe evstwhex 04 rS rA rB 0 1 1 0 0 1 1 0 0 0 0 EVX evstwhex evstwho 04 rS rA UIMM 3 0 1 1 0 0 1 1 0 1 0 1 EVX...

Page 509: ...1 0 0 0 0 1 XL bclrl crand 19 0x13 crbD crbA crbB 0 1 0 0 0 0 0 0 0 1 XL crand crandc 19 0x13 crbD crbA crbB 0 0 1 0 0 0 0 0 0 1 XL crandc creqv 19 0x13 crbD crbA crbB 0 1 0 0 1 0 0 0 0 1 XL creqv cr...

Page 510: ...ddco adde 31 0x1F rD rA rB 0 0 1 0 0 0 1 0 1 0 0 X adde adde 31 0x1F rD rA rB 0 0 1 0 0 0 1 0 1 0 1 X adde addeo 31 0x1F rD rA rB 1 0 1 0 0 0 1 0 1 0 0 X addeo addeo 31 0x1F rD rA rB 1 0 1 0 0 0 1 0 1...

Page 511: ...1 1 1 1 0 1 1 0 X dcbtst dcbtstls 31 0x1F CT rA rB 0 0 1 0 0 0 0 1 1 0 0 X dcbtstls dcbz 31 0x1F rA rB 1 1 1 1 1 1 0 1 1 0 X dcbz divw 31 0x1F rD rA rB 0 1 1 1 1 0 1 0 1 1 0 X divw divw 31 0x1F rD rA...

Page 512: ...1 1 0 X mbar mcrxr 31 0x1F crfD 1 0 0 0 0 0 0 0 0 0 X mcrxr mfcr 31 0x1F rD 0 0 0 0 0 1 0 0 1 1 X mfcr mfmsr 31 0x1F rD 0 0 0 1 0 1 0 0 1 1 X mfmsr mfpmr 31 0x1F rD PMRN5 9 PMRN0 4 0 1 0 1 0 0 1 1 1...

Page 513: ...1 1 0 0 0 0 X sraw sraw 31 0x1F rS rA rB 1 1 0 0 0 1 1 0 0 0 1 X sraw srawi 31 0x1F rS rA SH 1 1 0 0 1 1 1 0 0 0 0 X srawi srawi 31 0x1F rS rA SH 1 1 0 0 1 1 1 0 0 0 1 X srawi srw 31 0x1F rS rA rB 1 0...

Page 514: ...x1F rD rA 0 0 1 1 0 0 1 0 0 0 0 X subfze subfze 31 0x1F rD rA 0 0 1 1 0 0 1 0 0 0 1 X subfze subfzeo 31 0x1F rD rA 1 0 1 1 0 0 1 0 0 0 0 X subfzeo subfzeo 31 0x1F rD rA 1 0 1 1 0 0 1 0 0 0 1 X subfzeo...

Page 515: ...nemonic add 0 1 1 1 1 1 rD rA rB 0 1 0 0 0 0 1 0 1 0 0 X add add 0 1 1 1 1 1 rD rA rB 0 1 0 0 0 0 1 0 1 0 1 X add addc 0 1 1 1 1 1 rD rA rB 0 0 0 0 0 0 1 0 1 0 0 X addc addc 0 1 1 1 1 1 rD rA rB 0 0 0...

Page 516: ...rS rA 0 0 0 0 0 1 1 0 1 0 1 X cntlzw dcba 0 1 1 1 1 1 rA rB 1 0 1 1 1 1 0 1 1 0 X dcba dcbf 0 1 1 1 1 1 rA rB 0 0 0 1 0 1 0 1 1 0 X dcbf dcbi 0 1 1 1 1 1 rA rB 0 1 1 1 0 1 0 1 1 0 X dcbi dcblc 0 1 1...

Page 517: ...lhaux lhax 0 1 1 1 1 1 rD rA rB 0 1 0 1 0 1 0 1 1 1 X lhax lhbrx 0 1 1 1 1 1 rD rA rB 1 1 0 0 0 1 0 1 1 0 X lhbrx lhzux 0 1 1 1 1 1 rD rA rB 0 1 0 0 1 1 0 1 1 1 X lhzux lhzx 0 1 1 1 1 1 rD rA rB 0 1 0...

Page 518: ...rA rB 0 1 1 0 0 1 1 1 0 0 1 X orc slw 0 1 1 1 1 1 rS rA rB 0 0 0 0 0 1 1 0 0 0 0 X slw slw 0 1 1 1 1 1 rS rA rB 0 0 0 0 0 1 1 0 0 0 1 X slw sraw 0 1 1 1 1 1 rS rA rB 1 1 0 0 0 1 1 0 0 0 0 X sraw sraw...

Page 519: ...1 0 1 0 0 0 1 X subfo subfze 0 1 1 1 1 1 rD rA 0 0 1 1 0 0 1 0 0 0 0 X subfze subfze 0 1 1 1 1 1 rD rA 0 0 1 1 0 0 1 0 0 0 1 X subfze subfzeo 0 1 1 1 1 1 rD rA 1 0 1 1 0 0 1 0 0 0 0 X subfzeo subfzeo...

Page 520: ...1 0 0 0 0 1 rD rA D D lwzu mulli 0 0 0 1 1 1 rD rA SIMM D mulli ori 0 1 1 0 0 0 rS rA UIMM D ori oris 0 1 1 0 0 1 rS rA UIMM D oris stb 1 0 0 1 1 0 rS rA D D stb stbu 1 0 0 1 1 1 rS rA D D stbu sth 1...

Page 521: ...rB 0 1 0 1 1 1 0 1 0 0 1 EFX efddiv efdmul 0 0 0 1 0 0 rD rA rB 0 1 0 1 1 1 0 1 0 0 0 EFX efdmul efdnabs 0 0 0 1 0 0 rD rA 0 1 0 1 1 1 0 0 1 0 1 EFX efdnabs efdneg 0 0 0 1 0 0 rD rA 0 1 0 1 1 1 0 0 1...

Page 522: ...0 0 EVX evabs evaddiw 0 0 0 1 0 0 rD UIMM rB 0 1 0 0 0 0 0 0 0 1 0 EVX evaddiw evaddsmiaaw 0 0 0 1 0 0 rD rA 1 0 0 1 1 0 0 1 0 0 1 EVX evaddsmiaaw evaddssiaaw 0 0 0 1 0 0 rD rA 1 0 0 1 1 0 0 0 0 0 1 E...

Page 523: ...0 1 0 0 1 0 1 1 0 EVX evfsctuf evfsctui 0 0 0 1 0 0 rD rB 0 1 0 1 0 0 1 0 1 0 0 EVX evfsctui evfsctuiz 0 0 0 1 0 0 rD rB 0 1 0 1 0 0 1 1 0 0 0 EVX evfsctuiz evfsdiv 0 0 0 1 0 0 rD rA rB 0 1 0 1 0 0 0...

Page 524: ...rA rB 0 1 0 0 0 1 0 1 1 0 0 EVX evmergehi evmergehilo 0 0 0 1 0 0 rD rA rB 0 1 0 0 0 1 0 1 1 1 0 EVX evmergehilo evmergelo 0 0 0 1 0 0 rD rA rB 0 1 0 0 0 1 0 1 1 0 1 EVX evmergelo evmergelohi 0 0 0 1...

Page 525: ...D rA rB 1 0 1 1 0 1 0 1 1 0 1 EVX evmhogsmian evmhogumiaa 0 0 0 1 0 0 rD rA rB 1 0 1 0 0 1 0 1 1 0 0 EVX evmhogumiaa evmhogumian 0 0 0 1 0 0 rD rA rB 1 0 1 1 0 1 0 1 1 0 0 EVX evmhogumian evmhosmf 0 0...

Page 526: ...rA rB 1 0 1 1 1 0 0 0 1 0 0 EVX evmwhusianw evmwlumi 0 0 0 1 0 0 rD rA rB 1 0 0 0 1 0 0 1 0 0 0 EVX evmwlumi evmwlumia 0 0 0 1 0 0 rD rA rB 1 0 0 0 1 1 0 1 0 0 0 EVX evmwlumia evmwlumiaaw 0 0 0 1 0 0...

Page 527: ...1 1 0 EVX evslwi evsplatfi 0 0 0 1 0 0 rD SIMM 0 1 0 0 0 1 0 1 0 1 1 EVX evsplatfi evsplati 0 0 0 1 0 0 rD SIMM 0 1 0 0 0 1 0 1 0 0 1 EVX evsplati evsrwis 0 0 0 1 0 0 rD rA UIMM 0 1 0 0 0 1 0 0 0 1 1...

Page 528: ...1 0 1 0 0 rS rA SH MB ME Rc M rlwimi rlwinm 0 1 0 1 0 1 rS rA SH MB ME 0 M rlwinm rlwinm 0 1 0 1 0 1 rS rA SH MB ME 1 M rlwinm rlwnm 0 1 0 1 1 1 rS rA rB MB ME Rc M rlwnm rlwnm 0 1 0 1 1 1 rS rA rB M...

Page 529: ...0 0 0 0 0 1 XL crxor isync 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 XL isync mcrf 0 1 0 0 1 1 crfD crfS 0 0 0 0 0 0 0 0 0 0 XL mcrf rfci 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 XL rfci rfi 0 1 0 0 1 1 0 0 0 0 1 1 0 0...

Page 530: ...Opcode Listings PowerPC e500 Core Family Reference Manual Rev 1 D 50 Freescale Semiconductor...

Page 531: ...e e500v1 and e500v2 cores The coverage of Book E and Freescale Book E MMU architecture formerly in Chapter 13 Cache and MMU Background was removed See the EREF A reference for Freescale Book E and the...

Page 532: ...ters Deleted MCSR GL_CI from Table 5 4 Also removed column Recoverable in same table Section 5 7 Interrupt Definitions Deleted references to ESR AP which is not implemented on the e500 Chapter 9 Timer...

Page 533: ...aching allowed loads only if the two loads are to different 32 byte address granules with Newer non guarded caching allowed loads can bypass older non guarded caching allowed loads Chapter 12 Memory M...

Page 534: ...PowerPC e500 Core Family Reference Manual Rev 1 E 4 Freescale Semiconductor Revision History...

Page 535: ...tion select APU 3 25 3 60 machine check interrupt APU 3 63 5 2 see also Interrupt handling interrupt types machine check interrupt performance monitor APU 3 60 3 61 5 33 7 2 signal processing engine S...

Page 536: ...quired bit M bit 11 12 global signaling M bit and snooping 11 12 instruction cache coherency model 11 8 11 11 address aliasing errors 11 8 maintaining in power down mode 6 3 see also Memory cache acce...

Page 537: ...2 data address compare 8 9 instruction address compare 8 7 instruction complete debug event 8 12 interrupt taken debug event 8 13 return debug event 8 13 trap debug event 8 11 unconditional debug even...

Page 538: ...12 2 12 12 12 20 12 22 12 23 12 24 trap instr exceptions program interrupt 5 6 5 12 5 24 Execution model self modifying code 3 17 Execution synchronization 3 11 Execution timing branch instructions 4...

Page 539: ...d APUs embedded single precision floating point SPFP APUs 5 3 machine check interrupt APU 5 2 see also Auxiliary processing units APUs signal processing engine SPE APU 5 3 Freescale Book E implementat...

Page 540: ...ngle precision floating point APUs 3 58 store serialization 4 16 system linkage 3 26 3 40 system register instruction latencies 4 31 TLB management instructions 3 41 12 17 12 24 synchronization requir...

Page 541: ...idation protection 12 12 see also Memory management unit MMU TLBs isel instruction select APU 3 25 3 60 ISI instruction storage interrupt 5 20 see also Interrupt handling Issue stage see Execution tim...

Page 542: ...nt algorithm true LRU 12 10 structure 12 9 L2 TLB arrays programmable 12 8 replacement algorithm general 12 13 replacement algorithm hints for round robin TLB0 12 13 structure 12 11 TLB0 4 Kbyte page...

Page 543: ...ing for power savings 6 3 PLRU algorithm 11 25 see also Caches operation block replacement PMC0 3 performance monitor counter registers 2 57 7 8 PMGC0 global control register 0 1 31 2 53 7 4 PMLCa0 PM...

Page 544: ...ntrol 0 PMGC0 7 4 global control register 0 PMGC0 1 31 2 53 local control A PMLCa0 PMLCa3 2 55 7 5 local control B PMLCb0 PMLCb3 2 56 7 6 PMR encodings 3 61 user counter registers UPMC0 3 2 58 7 9 use...

Page 545: ...execution synchronization 3 11 general A 1 memory instructions 3 30 timing considerations 4 17 4 18 primitives A 2 compare and swap A 4 fetch and add A 3 fetch and AND A 3 fetch and no op A 2 fetch a...

Page 546: ...47 UPMC0 3 user performance monitor counter registers 2 58 7 9 UPMGC0 user global control register 0 2 54 7 5 UPMLCa0 UPMLCa3 user performance monitor local control A registers 2 56 UPMLCa0 UPMLCa3 us...

Page 547: ...Debug Support 8 Part II e500 Core Complex II Timer Facilities 9 Auxiliary Processing Units APUs 10 L1 Caches 11 Memory Management Units 12 Core Complex Bus CCB 13 Appendix A Programming Examples A Ap...

Page 548: ...r 8 Debug Support II Part II e500 Core Complex 9 Timer Facilities 10 Auxiliary Processing Units APUs 11 L1 Caches 12 Memory Management Units 13 Core Complex Bus CCB A Appendix A Programming Examples B...

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