PowerPC e500 Core Family Reference Manual, Rev. 1
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Freescale Semiconductor
Instruction Model
guaranteed to have returned the value stored by the first processor’s stwcx. (in the absence of other
stores to the given location).
3.3.1.7.1
Reservations
The ability to emulate an atomic operation using lwarx and stwcx. is based on the conditional
behavior of stwcx., the reservation set by lwarx, and the clearing of that reservation if the target
location is modified by another processor or mechanism before the stwcx. performs its store.
A reservation is held on an aligned unit of real memory called a reservation granule. The size of
the reservation granule is implementation-dependent, but is a multiple of 4 bytes for lwarx. The
reservation granule associated with effective address EA contains the real address to which EA
maps. (‘real_addr(EA)’ in the RTL for the load and reserve and store conditional instructions
stands for ‘real address to which EA maps.’) When one processor holds a reservation and another
processor performs a store, the first processor’s reservation is cleared if the store affects any bytes
in the reservation granule.
NOTE
One use of lwarx and stwcx. is to emulate a compare and swap
primitive like that provided by the IBM System/370 compare and
swap instruction, which checks only that the old and current values of
the word being tested are equal, with the result that programs that use
such a compare and swap to control a shared resource can err if the
word has been modified and the old value is subsequently restored.
The use of lwarx and stwcx. improves on such a compare and swap
because the reservation reliably binds lwarx and stwcx. together. The
reservation is always lost if the word is modified by another processor
or mechanism between the lwarx and stwcx., so the stwcx. never
succeeds unless the word has not been stored into (by another
processor or mechanism) since the lwarx.
A processor has at most one reservation at any time. Book E states that a reservation is established
by executing a lwarx and is lost (or may be lost, in the case of the fourth and fifth bullets) if any
of the following occurs.
•
The processor holding the reservation executes another lwarx; this clears the first
reservation and establishes a new one.
•
The processor holding the reservation executes any stwcx., regardless of whether the
specified address matches that of the lwarx.
•
Another processor executes a store or dcbz to the same reservation granule.
•
Another processor executes a dcbtst, dcbst, or dcbf to the same reservation granule;
whether the reservation is lost is undefined.
Summary of Contents for PowerPC e500 Core
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