Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
1-6 Freescale Semiconductor
Core Complex Overview
Machine Check Interrupt (rfmci) instruction. See Section 1.8, “Interrupts and
Exception Handling.”
— Single-precision embedded scalar and vector floating-point APUs. These instructions
are listed in Table 1-4 .
— Signal processing engine APU (SPE APU). Note that the SPE is not a separate unit; SPE
computational and logical instructions are executed in the simple and multiple-cycle
units used by all other computational and logical instructions, and 64-bit loads and stores
are executed in the common LSU.
Figure 1-1 shows how execution logic for SU1, the
MU, and the LSU is replicated to support operations on the upper halves of the GPRs.
Note that the SPE APU and the two single-precision floating-point APUs were combined in the
original implementation of the e500 v1, as shown in
Figure 1-2 .
The e500 register set is modified as follows:
– GPRs are widened to 64 bits to support 64-bit load, store, and merge operations. Note
that the upper 32 bits are affected only by 64-bit instructions.
– A 64-bit accumulator (ACC) has been added.
– The signal processing and embedded floating-point status and control register
(SPEFSCR) provides interrupt control and status for SPE and embedded
floating-point instructions.
These registers are shown in Figure 1-7 . SPE instructions are grouped as follows:
– Single-cycle integer add and subtract with the same latencies for SPE APU
operations as for the 32-bit equivalent
– Single-cycle logical operations
– Single-cycle shift and rotates
– Four-cycle integer pipelined multiplies
– 4-, 11-, 19-, and 35-cycle integer divides
– If rA or rB is zero, a floating-point divide takes 4 cycles; all other cases take 29 cycles.
– 4-cycle SIMD pipelined multiply-accumulate (MAC)
– 64-bit accumulator for no-stall MAC operations
Vector and Floating-Point APUs e500 v1 e500 v2
Original SPE
Definition
SPE vector instructions ev … √ √
Vector single-precision floating-point evfs … √ √
Scalar single-precision floating-point efs … √ √
Scalar double-precision floating-point efd … √
Figure 1-2. Vector and Floating-Point APUs