Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-7
Changing a value in certain system registers and invalidating TLB entries can have the side effect
of altering the context in which data addresses and instruction addresses are interpreted, and in
which instructions are executed. For example, changing MSR[IS] from 0 to 1 has the side effect
of changing address space. These effects need not occur in program order (that is, the strict order
in which they occur in the program) and therefore may require explicit synchronization by
software.
An instruction that alters the context in which data addresses or instruction addresses are
interpreted, or in which instructions are executed, is called a context-altering instruction. This
section covers all of the context-altering instructions. The software synchronization required for
each is shown in
Table 3-3 and Table 3-5 .
A context-synchronizing interrupt (that is, any interrupt except non-recoverable machine check)
can be used instead of a context-synchronizing instruction. If it is, references in this section to the
synchronizing instruction should be interpreted as meaning the instruction at which the interrupt
occurs. If no software synchronization is required either before or after a context-altering
instruction, the phrase ‘the synchronizing instruction before (or after) the context-altering
instruction’ should be interpreted as meaning the context-altering instruction itself.
The synchronizing instruction before the context-altering instruction ensures that all instructions
up to and including that synchronizing instruction are fetched and executed in the context that
existed before the alteration. The synchronizing instruction after the context-altering instruction
ensures that all instructions after that synchronizing instruction are fetched and executed in the
context established by the alteration. Instructions after the first synchronizing instruction, up to
and including the second synchronizing instruction, may be fetched or executed in either context.
If a sequence of instructions contains context-altering instructions and contains no instructions that
are affected by any of the context alterations, no software synchronization is required within the
sequence.
Sometimes advantage can be taken of the fact that certain instructions that occur naturally in the
program, such as the rfi at the end of an interrupt handler, provide the required synchronization.
No software synchronization is required before altering the MSR (except when altering the WE
bit) because mtmsr is execution synchronizing. No software synchronization is required before
most other alterations shown in
Table 3-5 , because all instructions before the context-altering
instruction are fetched and decoded before the context-altering instruction is executed. (The
processor must determine whether any of the preceding instructions are context-synchronizing.)