Debug Support
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor
8-13
8.4.6
Interrupt Taken Debug Event
An interrupt taken debug event occurs if DBCR0[IRPT] is set (interrupt taken debug events are
enabled) and a noncritical interrupt occurs. Interrupt taken debug events can occur regardless of
the value of MSR[DE].
Only noncritical interrupts can cause an interrupt taken debug event because all critical interrupts
automatically clear DE and thus would always prevent the associated debug interrupt from
occurring precisely. Also, debug interrupts themselves are critical interrupts, so any additional
debug interrupt (for a second debug event) would always set the additional DBSR[IRPT]
exception when it entered the debug interrupt handler. At this point, the debug interrupt handler
could not determine if the second interrupt taken debug event was related to the original event.
When an interrupt taken debug event occurs, IRPT is set to capture the debug exception. If DE is
zero, DBSR[IDE] is also set to record the imprecise debug event. If DE is set at the time of the
event, the following occurs:
•
A debug interrupt occurs immediately if no higher priority exception caused an interrupt.
•
CSRR0 is set to the address of the noncritical interrupt vector that caused the event. No
instructions at the noncritical interrupt handler are executed.
If debug interrupts are disabled when the event occurs, no interrupt is generated. However, if the
debug exception has not been reset by clearing DBSR[IRPT], a delayed debug interrupt occurs
when interrupts are reenabled (MSR[DE] is set). In this case, CSRR0 contains the address of the
instruction following the one that set DE. The interrupt handler can observe DBSR[IDE] to
determine how to interpret CSRR0.
8.4.7
Return Debug Event
A return debug event occurs if DBCR0[RET] is set (enabling return debug events) and an attempt
is made to execute an rfi. Results from executing an rfci while RET is set are implementation
dependent; the e500 does the following:
•
If MSR[DE] is set, a debug interrupt is generated.
•
If DE is cleared, no debug interrupt is generated and no debug event is logged.
When a return debug event occurs, DBSR[RET] is set to capture the debug exception. If MSR[DE]
is cleared when rfi executes (before the MSR is updated by the rfi), DBSR[IDE] is also set to
record the imprecise debug event. If DE is set at the time of the return debug exception, the
following events occur:
•
A debug interrupt is taken immediately (unless the rfi or rfci causing the event clears
MSR[DE] or a higher priority exception has caused an interrupt).
•
CSRR0 is loaded with the address of the instruction that would have executed next had the
interrupt not occurred.
Summary of Contents for PowerPC e500 Core
Page 1: ...PowerPC e500 Core Family Reference Manual Supports e500v1 e500v2 E500CORERM Rev 1 4 2005...
Page 36: ...PowerPC e500 Core Family Reference Manual Rev 1 xxxvi Freescale Semiconductor...
Page 38: ...PowerPC e500 Core Family Reference Manual Rev 1 Part I 2 Freescale Semiconductor...
Page 332: ...PowerPC e500 Core Family Reference Manual Rev 1 Part II 2 Freescale Semiconductor...
Page 530: ...Opcode Listings PowerPC e500 Core Family Reference Manual Rev 1 D 50 Freescale Semiconductor...
Page 534: ...PowerPC e500 Core Family Reference Manual Rev 1 E 4 Freescale Semiconductor Revision History...
