Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Memory Management Units
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-17
The G bit is ignored for instruction fetches, and instructions are speculatively fetched from
guarded pages. To prevent speculative fetches from pages that do not contain instructions and are
guarded, the page should be also designated as no-execute (with the UX/SX page permission bits
cleared).
12.3.6 TLB Entry Field Definitions
Table 12-4 summarizes the fields of e500 TLB entries. Note that all of these fields are defined at
the Freescale Book E level. See the EREF for the definition of TLB fields at the Freescale Book E
level.
12.4 TLB Instructions—Implementation
As described in the Cache and MMU Background chapter of the EREF, the TLBs are accessed
indirectly through MMU assist (MAS) registers. Software can write and read the MMU assist
registers with mtspr and mfspr instructions. These registers contain information related to
reading and writing a given entry within the TLBs. For example, data is read from the TLBs into
the MAS registers with a TLB Read Entry (tlbre) instruction, and data is written to the TLBs from
the MAS registers with a TLB Write Entry (tlbwe) instruction.
Table 12-4. TLB Entry Bit Definitions for e500
Field Comments
V Valid bit for entry
TS Translation address space (compared with AS bit of the current access)
TID[0–7] Translation ID (compared with PID0, PID1, PID2 or TIDZ (all zeros))
EPN[0–19] Effective page number (compared with EA[32–51] for 4-Kbyte pages)
RPN[0–19] (e500v1);
RPN[0–23] (e500v2)
Real page number
Translated address RA[32–51] for 4-Kbyte pages for e500v1
Translated address RA[28–51] for 4-Kbyte pages for e500v1
SIZE[0–3] Encoded page size
0000 Reserved
0001 4 Kbyte
0010 16 Kbyte
0011 64 Kbyte
0100 256 Kbyte
0101 1 Mbyte
0110 4 Mbyte
0111 16 Mbyte
1000 64 Mbyte
1001 256 Mbyte
1010 1 Gbyte (for e500v2 only)
1011 4 Gbyte (for e500v2 only)
all others—reserved
PERMIS[0–5] Supervisor execute, write, and read permission bits, and user execute, write, and read permission bits.
WIMGE Memory/cache attributes (write-through, cache-inhibit, memory coherence required, guarded, endian)
X0, X1 Extra system attribute bits (for definition by system software)
U0–U3 User attribute bits—used only by software. These bits exist in the L2 MMU TLBs only (TLB1 and TLB0)
IPROT Invalidation protection (exists in TLB1 only)