Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Memory Management Units
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-19
12.4.2 TLB Write Entry (tlbwe) Instruction
The tlbwe instruction causes the contents of certain fields of the MAS registers (MAS0, MAS1,
MAS2, and MAS3) to be written into a single TLB entry in the L2 MMU. Execution of the tlbwe
instruction on the e500v2 core also causes the upper 4 bits of the RPN that reside in MAS7 to be
written to the selected TLB entry. The entry written is specified by the TLBSEL, ESEL, and EPN
fields of the MAS0, and MAS2 registers.
The following RTL describes the e500 core complex tlbwe implementation:
tlb_entry_id = MAS0(TLBSEL, ESEL) || MAS2(EPN)
L2MMU(tlb_entry_id) = MAS0, MAS1, MAS2, MAS3, (and MAS7 on e500v2)
Note that when an L2 TLB entry is written, it may be displacing an already valid entry in the same
L2 TLB location (a victim). If a valid L1 TLB entry corresponds to the L2 MMU victim entry, that
L1 TLB entry is automatically invalidated. See the EREF for synchronization requirements
defined at the Freescale Book E level for the use of tlbwe.
12.4.2.1 Writing to the TLB1 Array
TLB1 can be written by first writing the necessary information into MAS0–MAS3 (and MAS7 for
the e500v2) using mtspr and then executing the tlbwe instruction. To write an entry into TLB1,
MAS0[TLBSEL] must = 01, and MAS0[ESEL] must point to the desired entry. When the tlbwe
instruction is executed, the TLB entry information stored in MAS0–MAS3 (and MAS7 for the
e500v2) is written into the selected TLB entry in the TLB1 array.
12.4.2.2 Writing to the TLB0 Array
TLB0 can be written by first writing the necessary information into MAS0–MAS3 (and MAS7 for
the e500v2) using mtspr and then executing the tlbwe instruction. To write an entry into TLB0,
MAS0[TLBSEL] must = 00, MAS0[ESEL] must point to the desired way, and EPN[45–51] in
MAS2 must be loaded with the desired index. When the tlbwe instruction is executed, the TLB
entry information stored in MAS0–MAS3 (and MAS7 for the e500v2) is written into the selected
TLB entry in TLB0.
12.4.3 TLB Search (tlbsx) Instruction—Searching the TLB1 and
TLB0 Arrays
The tlbsx instruction updates the MAS registers conditionally based on the success or failure of a
TLB lookup in the L2 MMU. The lookup is controlled by the effective address provided by
GPR[rA] + GPR[rB] specified in the instruction encoding, as well as by the SAS and SPID0 search
fields in MAS6. The values placed into MAS0, MAS1, MAS2, MAS3, and optionally, MAS7
differ, depending on whether a successful or unsuccessful search occurred. See
Section 12.7.2,
“MAS Register Updates ,” for details on which MAS register fields are updated for these cases.