Freescale Semiconductor PowerPC e500 Core, Reference Manual

Page: 267 / 548

Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-15
instruction, but may not be recognized or reported until long after the processor has executed past
the instruction that caused the machine check. As such, machine check interrupts are not thought
of as synchronous or asynchronous nor as precise or imprecise.
The following general rules apply:
• No instruction after the one whose address is reported to the machine check interrupt
handler in MCSRR0 has begun execution.
• The instruction whose address is reported to the machine check interrupt handler in
MCSRR0 and all prior instructions may or may not have completed successfully. All
instructions certain to complete appear to have done so within the context existing before
the machine check interrupt. No further interrupts (other than possible additional machine
check interrupts) occur as a result of those instructions.
e500 machine check exceptions are specified in Table 5-8 .
If MSR[ME] is cleared, the processor enters checkstop state immediately on detecting the machine
check condition.
Table 5-8. e500 Machine Check Exception Sources
Source Signal Additional Enable Bits
Negative edge on machine check signal ( mcp) mcp HID0[EMCP]
Data cache parity error dcperr L1CSR0[CPE]
Instruction cache parity error icperr L1CSR1[ICPE]
Data cache push parity error dcp_perr L1CSR0[CPE]
Bus instruction address error bus_iaerr No enable bit
Bus read address error bus_raerr No enable bit
Bus write address error bus_waerr No enable bit
Bus instruction data bus error bus_iberr No enable bit
Read data bus error bus_rberr No enable bit
Write bus error bus_wberr No enable bit
Instruction parity error bus_iperr HID1[R1DPE], HID1[R2DPE] (depending on which bus the
instruction fetch arrived)
Read parity error
bus_rperr
HID1[R1DPE], HID1[R2DPE] (on whichever bus the data read
arrived)
Bus fault core_fault_in HID1[RFXE] = 1. This interrupt should not occur during normal
operation because RFXE should be zero and such errors shold
be reported instead by peripherals as external interrupts or
critical interrupts. For information about bus faults, see
Section 13.8, “Proper Reporting of Bus Faults .” For additional
information, see Section 2.10.2, “Hardware
Implementation-Dependent Register 1 (HID1) .”