Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Core Complex Overview
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 1-33
1.13.2 Memory Subsystem
Both Book E and the AIM version of the PowerPC architecture provide separate instruction and
data memory resources. The e500 provides additional cache control features, including cache
locking.
1.13.3 Exception Handling
Exception handling is generally the same as that defined in the AIM version of the PowerPC
architecture for the e500, with the following differences:
• Book E defines a new critical interrupt, providing an extra level of interrupt nesting. The
critical interrupt includes external critical and watchdog timer time-out inputs.
• The machine check exception differs from the Book E and from the AIM definition. It
defines the Return from Machine Check Interrupt instruction, rfmci, and two machine
check save/restore registers, MCSRR0 and MCSRR1.
• Book E processors can use IVPR and IVORs to set exception vectors individually, but they
can be set to the address offsets defined in the OEA to provide compatibility.
• Unlike the AIM version of the PowerPC architecture, Book E does not define a reset vector;
execution begins at a fixed virtual address, 0xFFFF_FFFC.
• Some Book E and e500-specific SPRs are different from those defined in the AIM version
of the PowerPC architecture, particularly those related to the MMU functions. Much of this
information has been moved to a new exception syndrome register (ESR).
• Timer services are generally compatible, although Book E defines a new decrementer auto
reload feature, the fixed-interval timer critical interrupt, and the watchdog timer interrupt,
which are implemented in the e500 core.
An overview of the interrupt and exception handling capabilities of the e500 core can be found in
Section 1.8, “Interrupts and Exception Handling.”
1.13.4 Memory Management
The e500 core implements a straightforward virtual address space that complies with the Book E
MMU definition, which eliminates segment registers and block address translation resources.
Book E defines resources for fixed 4-Kbyte pages and multiple, variable page sizes that can be
configured in a single implementation. TLB management is provided with new instructions and
SPRs.