Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
4-8 Freescale Semiconductor
Execution Timing
(except multiply and divide instructions) defined by the SPE and embedded
floating-point APUs, as follows:
– SU1 executes 32- and 64-bit SPE and floating-point logical instructions, simple
integer arithmetic, and bit manipulation instructions, such as merges and splats.
– SU2 executes a subset of the instructions that can be executed in SU1. These include
brinc and the embedded floating-point logical instructions, efsabs, efsnabs, efsneg,
efststeq, efststgt, and efststlt, and efdabs, efdnabs, efdneg, efdtsteq, efdtstgt, and
efdtstlt in the e500v2.
Most SU instructions execute in 1 cycle. Table 4-6 identifies which Book E instructions
execute in SU1 and SU2 and shows their latencies; Table 4-8 identifies which SPE and
floating-point APU instructions execute in SU1 and SU2 and shows their latencies.
Note that most SU instructions execute in 1 cycle, while some instructions (such as
mtspr and mfspr) take longer.
— Multiple-cycle IU (MU) executes integer multiplication and division instructions, and
addition, subtraction, multiplication, and division for all vector and scalar instructions.
NOTE
As suggested by Figure 4-1 , the MU and SU1 each have upper and
lower halves. Both halves are used for SPE and floating-point vector
instructions. Only the lower half is used by scalar instructions,
including embedded single-precision floating-point instructions.
The execution unit executes the instruction (perhaps over multiple cycles), writes results on
its result bus, and notifies the CQ when the instruction finishes. The execution unit reports
any exceptions to the completion stage. Instruction-generated exceptions are not taken until
the excepting instruction is next to retire.
Most integer instructions have a 1-cycle latency, so results of these instructions are
available 1 clock cycle after an instruction enters the execution unit. The LSU and MU are
pipelined, as shown in
Figure 4-4 .
• The complete and write-back stages maintain the correct architectural machine state and
commit results to the architecture-defined registers in the proper order. If completion logic
detects an instruction containing an exception status or a mispredicted branch, all following
instructions are cancelled, their execution results in rename registers are discarded, and the
correct instruction stream is fetched.
The complete stage ends when the instruction is retired. Two instructions can be retired per
clock cycle. If no dependencies exist, as many as two instructions are retired in program
order.
Section 4.7.4, “Completion Unit Resource Requirements ” describes completion
dependencies.
The write-back stage occurs in the clock cycle after the instruction is retired.