Freescale Semiconductor PowerPC e500 Core, Reference Manual

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L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-21
11.4.4.1 Effects of Other Cache Instructions on Locked Lines
The following cache instructions do not affect the state of a cache line's lock bit:
• dcbt (CT = 0)
• dcbtst (CT = 0)
If dcbt is performed to a line that is locked in the cache in the modified or exclusive state, dcbt
takes no action. However, if the line is invalid, and therefore not locked, dcbt causes a state
change.
If a dcbtst (CT=0) is performed to a line that is locked in the cache in the modified or exclusive
state, dcbtst takes no action. If the line is invalid, and therefore not locked, dcbtst causes a state
change.
The following cache instructions are treated as stores and may cause the invalidation and
unlocking of a cache line in another processor in a multiprocessor system:
• dcba
• dcbz
In implementations with an L2 cache, the following instructions, when directed to the L2 cache
(CT = 1), flush/invalidate and unlock a line in the L1 data cache of the current processor:
• dcbt
• dcbtst
• dcbtls
• dcbtstls
• icbt
• icbtls
The following cache instructions flush/invalidate and unlock a line in the cache of the current
processor, and may also flush/invalidate and unlock a cache line in other processors in a
multiprocessor system:
• dcbf
• dcbst
• icbi
• dcbi
11.4.4.2 Flash Clearing of Lock Bits
The core complex allows flash clearing of the instruction and data cache lock bits under software
control. Each cache’s lock bits can be independently flash cleared through the CLFC control bits
in L1CSR0 and L1CSR1.