Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
3-10 Freescale Semiconductor
Instruction Model
3.2.3.2 Synchronization with tlbwe and tlbivax Instructions
The following sequence shows why, for data accesses, it is necessary to ensure that all memory
accesses due to instructions before the tlbwe or tlbivax have completed to a point at which they
mtspr (PID) None CSI
4 2
mtspr (TCR) None None
9
mtspr (TSR) None None
9
rfci None None
rfi None None
sc None None
tlbivax None CSI
4
or msync
10,11
tlbwe None CSI
4
or msync
10,11
wrtee, wrteei None None
1
1
The effect of changing MSR[EE] or MSR[CE] is immediate.
If mtmsr , wrtee , or wrteei clears MSR[EE], an external input, decrementer or fixed-interval timer interrupt does not occur after
the instruction is executed.
If mtmsr , wrtee , or wrteei changes MSR[EE] from 0 to 1 when an external input, decrementer, fixed-interval timer, or higher
priority enabled exception exists, the corresponding interrupt occurs immediately after the mtmsr , wrtee , or wrteei is executed,
and before the next instruction executes in the program that set MSR[EE].
2
The alteration must not cause an implicit branch in real address space. Thus the real address of the context-altering instruction
and of each subsequent instruction, up to and including the next context-synchronizing instruction, must be independent of
whether the alteration has taken effect.
3
A context-synchronizing instruction is required after altering MSR[ME] to ensure that the alteration takes effect for subsequent
machine check interrupts, which may not be recoverable and so may not be context-synchronizing.
4
CSI indicates any context-synchronizing instruction (that is, sc , isync , rfci , rfmci , or rfi ).
5
Synchronization requirements for changing the wait state enable are implementation-dependent.
6
For more information about synchronization requirements with mtmsr ( WE ), see Section 6.4.1, “Software Considerations for
Power Management.”
7
CSI indicates any context-synchronizing instruction (that is, sc , isync , rfci , rfmci , or rfi ).
8
Synchronization requirements for changing any debug facility registers are implementation-dependent.
9
The elapsed time between the DEC reaching zero, or the transition of the selected time base bit for the fixed-interval or
watchdog timer, and the signalling of the decrementer, fixed-interval timer, or watchdog timer exception is not defined.
10
For data accesses, the context-synchronizing instruction before the tlbwe or tlbivax instruction ensures that all accesses due
to preceding instructions have completed to a point at which they have reported all exceptions they will cause. See
Section 3.2.3.2, “Synchronization with tlbwe and tlbivax Instructions.”
11
The context-synchronizing instruction after tlbwe or tlbivax ensures that subsequent accesses (data and instruction) use the
updated value in the affected TLB entries. It does not ensure that all accesses previously translated by the TLB entries being
updated have completed with respect to memory; if these completions must be ensured,
tlbwe or tlbivax must be followed by
an msync and by a context-synchronizing instruction. See Section 3.2.3.2, “Synchronization with tlbwe and tlbivax
Instructions.”
Table 3-5. Instruction Fetch and/or Execution Synchronization Requirements (continued)
Context Altering Instruction or Event Required Before Required After Notes