Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
4-18 Freescale Semiconductor
Execution Timing
The Book E architecture allows an implementation to support several classes of storage ordering,
selected by the MO field of the mbar instruction. The core complex supports two classes for
system flexibility.
The e500 implements two variations of mbar, as follows:
• When MO = 0, mbar behaves as defined by Book E.
• When MO = 1, mbar is a weaker, faster memory barrier; the e500 executes it as a pipelined
or flowing ordering barrier for potentially higher performance. This ordering barrier flows
along with pre- and post-mbar memory transactions through the memory hierarchy (L1
cache, bus, and system). On the bus, this ordering barrier is issued as an ORDER command
(if HID1[ABE] is set).
mbar ensures that all data accesses caused by previous instructions complete before any
caused by subsequent instructions. This order is seen by all mechanisms. However, unlike
msync and mbar with MO = 0, subsequent instructions can complete without waiting for
mbar to perform its address bus tenure. This provides a faster way to order data accesses.
4.4 Execution
The following sections describe instruction execution behavior within each of the respective
execution units in the e500.
4.4.1 Branch Unit Execution
When branch or trap instructions change program flow, the IQ must be reloaded with the target
instruction stream. Previously issued instructions continue executing while the new instruction
stream makes its way into the IQ. Depending on whether target instructions are cached,
opportunities may be missed to execute instructions.
The e500 minimizes penalties associated with flow control operations by features such as the
branch target buffer (BTB), BTB locking, dynamic branch prediction, speculative link and counter
registers, and nonblocking caches.
4.4.1.1 Branch Instructions and Completion
Branch instructions are not folded on the e500; all branch instructions receive a CQ entry (and
CRF and GPR renames) at dispatch and must write back in program order.