Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
12-22 Freescale Semiconductor
Memory Management Units
12.4.4.2 Invalidate All Address Encoding for tlbivax Instruction
Bit 61 of the tlbivax effective address is interpreted as the INV_ALL command. If this bit is set,
it indicates that the invalidate operation should completely invalidate all entries of either TLB1 or
TLB0 as indicated by the TLBSEL field, and invalidate all corresponding L1 TLB entries. Note
that entries in TLB1 can be protected from this type of invalidation by setting the IPROT bit as
described in
Section 12.3.2.1, “IPROT Invalidation Protection in TLB1 .”
12.4.4.3 TLB Invalidate Broadcast Enabling
In addition to invalidating the local matching TLB entries, the tlbivax instruction operation is also
broadcast on the bus (causing a TLBINV address-only transaction) according to the value of the
ABE (address broadcast enable) bit in the HID1 register as follows:
• If HID1[ABE] = 0, tlbivax instructions are not broadcast.
• If HID1[ABE] = 1, tlbivax instructions are broadcast.
12.4.5 TLB Synchronize (tlbsync) Instruction
The tlbsync instruction causes a TLBSYNC transaction on the CCB. This transaction is retried if
any processor, including the one that executed the tlbsync instruction, has pending memory
accesses that were issued before any previous tlbivax instructions were completed. This
instruction effectively synchronizes the invalidation of TLB entries; tlbsync does not complete
until all memory accesses caused by instructions issued before an earlier tlbivax instruction have
completed.
12.5 TLB Entry Maintenance—Details
The TLB entries of the e500 core complex must be loaded and maintained by the system software,
including performing the required table search operations in memory. However, the e500 provides
some hardware assistance for these software tasks. Note that the system software cannot directly
access the L1 TLBs, and the L1 TLBs are completely and automatically maintained in hardware
as a subset of the contents of the L2 TLBs.
In addition to the resources described in Table 12-1 , hardware assistance on the core complex for
maintenance of TLB entries includes:
• Automatic loading of MAS0–2 based on the default values in MAS4 on TLB miss
exceptions. This automatically generates most fields of the required TLB entry on a miss.
Thus software should load MAS4 with likely values to be used in the event of a TLB miss
condition.
• Automatic loading of the data exception address register (DEAR) with the effective address
of the load, store, or cache management instruction that caused an alignment, data TLB
miss (data TLB error interrupt), or permissions violation (DSI interrupt).