Freescale Semiconductor PowerPC e500 Core, Reference Manual

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L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-13
11.3.4 WIMGE Settings and Effect on L1 Caches
All instruction and data accesses are performed under control of the WIMGE bits. This section
describes how WIMGE bit settings affect the behavior of the L1 caches. For more information see
the EREF.
11.3.4.1 Write-Back Stores
A write-back store that hits a line that is already in exclusive state is immediately stored to the line;
the state is changed to modified. If a write-back store hits a line that is already in the modified state,
it is immediately stored to the line, and the line stays as modified.
11.3.4.2 Write-Through Stores
A write-through store operation (WIMGE = 0b10xxx) may hit an exclusive cache line. In this
case, the store data is written into the data cache and the write-through store goes to the CCB as a
single-beat write. The cache line stays exclusive.
A write-through store may also hit in a cache line that is already in the modified state. This
situation normally occurs as a result of page table aliasing in which two effective addresses are
mapped to the same physical page, but with one mapped as write-through and the other mapped
as write-back (that is, non-write-through). In this case, the cache line remains in its current state,
the store data is written into the data cache, and the store goes to the CCB as a single-beat write.
11.3.4.3 Caching-Inhibited Loads and Stores
A caching-inhibited load or store (WIMGE = 0bx1xxx) that hits in the cache presents a cache
coherency paradox and is normally considered a programming error. If a caching-inhibited load
hits in the cache, the cache data is ignored and the load is provided from the CCB as a single-beat
read. If a caching-inhibited store hits in the cache, the cache may be altered but the store is
performed on the CCB anyway as a single-beat write.
11.3.4.4 Misaligned Accesses and the Endian (E) Bit
Misaligned accesses that cross page boundaries could cause data corruption if the two pages are not
set to have the same endianness (that is, one page is big endian while the other is little endian) and
the access is allowed. When this situation occurs, the core complex takes a DSI exception and sets
the BO (byte ordering) bit in the exception syndrome register (ESR) instead of performing the
accesses.
11.3.4.5 Speculative Accesses to Guarded Memory
There is no restriction on how the core complex performs instruction fetching from guarded
memory, if the memory area is marked as execute-permitted (UX/SX = 1) in the TLBs. Note that