Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-3
• Reservation station—A buffer between the issue and execute stages that allows instructions
to be issued even though resources necessary for execution or results of other instructions
on which the issued instruction may depend are not yet available.
• Retirement—Removal of a completed instruction from the completion queue at the end of
the completion stage. (In other documents, this is often called deallocation.)
• Speculative instruction—Any instruction that is currently behind an older branch
instruction that has not been resolved.
• Stage—Used in two different senses, depending on whether the pipeline is being discussed
as a physical entity or a sequence of events. As a physical entity, a stage can be viewed as
the hardware that handles operations on an instruction in that part of the pipeline. When
viewing the pipeline as a sequence of events, a stage is an element in the pipeline during
which certain actions are performed, such as decoding the instruction, performing an
arithmetic operation, or writing back the results. Typically, the latency of a stage is one
processor clock cycle. Some events, such as dispatch, write-back, and completion, happen
instantaneously and may be thought to occur at the end of a stage.
An instruction can spend multiple cycles in one stage; for example, a divide takes multiple
cycles in the execute stage.
An instruction can also be represented in more than one stage simultaneously, especially in
the sense that a stage can be seen as a physical resource. For example, when instructions
are dispatched, they are assigned a place in the CQ at the same time they are passed to the
issue queues.
• Stall—An occurrence when an instruction cannot proceed to the next stage. Such a delay is
initiated to resolve a data or resource hazard, that is, a situation in which a planned
instruction cannot execute in the proper clock cycle because data or resources needed to
process the instruction are not yet available.
• Superscalar—A superscalar processor is one that can issue multiple instructions
concurrently from a conventional linear instruction stream. In a superscalar
implementation, multiple instructions can execute in parallel at the same time.
• Throughput—The number of instructions processed per cycle. In particular, throughput
describes the performance of a multiple-stage pipeline where a sequence of instructions
may pass through with a throughput that is much faster than the latency of an individual
instruction. For example, in the four-stage multiple-cycle pipeline (MU), a series of mulli
instructions has a throughput of one instruction per clock cycle even though it takes 4 cycles
for one mulli instruction to execute.
• Write-back—Write-back (in the context of instruction handling) occurs when a result is
written into the architecture-defined registers (typically the GPRs). On the e500, write-back
occurs in the clock cycle after the completion stage. Results in the write-back buffer cannot
be flushed. If an exception occurs, results from previous instructions must write back
before the exception is taken.