Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
5-10 Freescale Semiconductor
Interrupts and Exceptions
5.5.1 Requirements for System Reset Generation
Book E does not specify a system reset interrupt as was defined in the AIM version of the
PowerPC architecture. On the e500, a system reset is initiated in one of the following ways:
• By asserting hreset, which resets the internal state of the core complex
• By writing a 1 to DBCR0[34], if MSR[DE] = 1
5.6 Interrupt Processing
Associated with each kind of interrupt is an interrupt vector, the address of the initial instruction
that is executed when an interrupt occurs.
Interrupt processing consists of saving a small part of the processor’s state in certain registers,
identifying the cause of the interrupt in another register, and continuing execution at the
corresponding interrupt vector location. When an exception exists that causes an interrupt to be
generated and it has been determined that the interrupt can be taken, the following steps are
performed:
1. SRR0 (for noncritical class interrupts) or CSRR0 (for critical class interrupts) or MCSRR0
for machine check interrupts is loaded with an instruction address that depends on the type
of interrupt; see the specific interrupt description for details.
2. The ESR or MCSR is loaded with information specific to the exception type. Note that
many interrupt types can only be caused by a single type of exception event, and thus do
not need nor use an ESR setting to indicate the cause of the interrupt.
Synchronous,
Imprecise
Imprecise interrupts may indicate the address of the instruction causing the exception that generated the interrupt
or some instruction after that instruction. When execution or attempted execution of an instruction causes an
imprecise interrupt, the following conditions exist at the interrupt point.
• SRR0 or CSRR0 addresses either the exception-causing instruction or some instruction following the
exception-causing instruction that generated the interrupt.
• An interrupt is generated such that all instructions preceding the instruction addressed by SRR0 or CSRR0
appear to have completed with respect to the executing processor.
• If context synchronization forces the imprecise interrupt due to an instruction that causes another exception
that generates an interrupt (for example, alignment or data storage interrupt), SRR0 addresses the
interrupt-forcing instruction, which may have partially executed (see
Section 5.9, “Partially Executed
Instructions ”).
• If execution synchronization forces an imprecise interrupt due to an execution-synchronizing instruction other than
msync or isync , SRR0 or CSRR0 addresses the interrupt-forcing instruction, which appears not to have begun
execution (except for its forcing the imprecise interrupt). If the interrupt is forced by msync or isync , SRR0 or
CSRR0 may address msync or isync , or the following instruction.
• If context or execution synchronization forces an imprecise interrupt, the instruction addressed by SRR0 or
CSRR0 may have partially executed (see Section 5.9, “Partially Executed Instructions ”). No instruction
following the instruction addressed by SRR0 or CSRR0 has executed.
Table 5-5. Asynchronous and Synchronous Interrupts (continued)
Class Description