Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Core Complex Overview
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 1-17
Because there are so many variables, unless otherwise specified, the instruction timing
examples in this chapter assume optimal performance and show the portion of the fetch
stage in which the instruction is in the instruction queue. The fetch1 and fetch2 stages are
primarily involved in retrieving instructions.
• The decode/dispatch stage fully decodes each instruction; most instructions are dispatched
to the issue queues (however, isync, rfi, sc, nops, and some other instructions do not go to
issue queues).
• The two issue queues, BIQ and GIQ, can accept as many as one and two instructions,
respectively, in a cycle. The behavior of instruction dispatch is covered in significant detail
in the e500 Software Optimization Guide. The following simplification covers most cases:
— Instructions dispatch only from the two lowest IQ entries—IQ0 and IQ1.
— A total of two instructions can be dispatched to the issue queues per clock cycle.
— Space must be available in the CQ for an instruction to decode and dispatch (this includes
instructions that are assigned a space in the CQ but not in an issue queue).
Dispatch is treated as an event at the end of the decode stage. The issue stage reads source
operands from rename registers and register files and determines when instructions are
latched into the execution unit reservation stations. Note that the e500 has 14 rename
registers, one for each completion queue entry, so instructions cannot stall because of a
shortage of rename registers.
The general behavior of the two issue queues is described as follows:
— The GIQ accepts as many as two instructions from the dispatch unit per cycle. SU1,
SU2, MU, and all LSU instructions (including 64-bit loads and stores) are dispatched to
the GIQ, shown in
Figure 1-6 .
Figure 1-6. GPR Issue Queue (GIQ)
Instructions can be issued out-of-order from the bottom two GIQ entries (GIQ1–GIQ0).
GIQ0 can issue to SU1, MU, and LSU. GIQ1 can issue to SU2, MU, and LSU.
Note that SU2 executes a subset of the instructions that can be executed in SU1. The
ability to identify and dispatch instructions to SU2 increases the availability of SU1 to
execute more computational-intensive instructions.
An instruction in GIQ1 destined for SU2 or the LSU need not wait for an MU
instruction in GIQ0 that is stalled behind a long-latency divide.
GIQ1
GIQ3
GIQ0
GIQ2
To SU2, MU, or LSU
From IQ0/IQ1
To SU1, MU, or LSU