Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-17
3.3.1.2 Load and Store Instructions
Load and store instructions are issued and translated in program order; however, the accesses can
occur out of order. Synchronizing instructions are provided to enforce strict ordering. The e500
supports load and store instructions as follows:
• Integer load instructions
• Integer store instructions
• Integer load and store with byte-reverse instructions
• Integer load and store multiple instructions
• Memory synchronization instructions
• SPE APU load and store instructions for reading and writing 64-bit GPRs. These are
described in
Section 3.8.1, “SPE and Embedded Floating-Point APUs .”
The e500 does not implement Book E floating-point load and store instructions.
Implementation Notes—The following describes how the e500 handles misalignment:
The e500 provides hardware support for misaligned memory accesses. It performs those accesses
within a single cycle if the operand lies within a double-word boundary. Misaligned memory
accesses that cross a double-word boundary degrade performance.
Although many misaligned memory accesses are supported in hardware, the frequent use of them
is discouraged because they can compromise the overall performance of the processor. Only one
outstanding misalignment at a time is supported, which means it is non-pipelined.
Accesses that cross a translation boundary can be restarted. That is, a misaligned access that
crosses a page boundary is completely restarted if the second portion of the access causes a page
fault. This can cause the first access to be repeated.
3.3.1.2.1 Self-Modifying Code
When a processor modifies any memory location that can contain an instruction, software must
ensure that the instruction cache is made consistent with data memory and that the modifications
are made visible to the instruction fetching mechanism. This must be done even if the cache is
disabled or if the page is marked caching-inhibited.
The following instruction sequence can be used to accomplish this when the instructions being
modified are in memory that is memory-coherency required and one processor both modifies the
instructions and executes them. (Additional synchronization is needed when one processor
modifies instructions that another processor will execute.)