Freescale Semiconductor PowerPC e500 Core, Reference Manual

Page: 397 / 548

Memory Management Units
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-7
12.2.3 Checking for TLB Entry Hit
Figure 12-3 shows the compare function used by the e500 to check the MMU structures for a hit
for the three virtual addresses that correspond to the instruction or data access (one virtual address
for each current PID register value). Note that this figure is functionally similar to the figure in the
EREF that shows the Book E algorithm, except that this figure shows that three PID values are
compared for each access.
A hit to multiple matching TLB entries is considered a programming error. If this occurs, the TLB
generates an invalid address and TLB entries may be corrupted (an exception is not reported).
Figure 12-3. Virtual Address and TLB-Entry Compare Process
12.2.4 Checking for Access Permissions
When a TLB entry matches with one of the three virtual addresses of an access, the permission bits
of the TLB entry are compared with attribute information of the access (read/write,
instruction/data, user/supervisor) to see if the access is allowed to that page. The checking of
permissions on the e500 functions as described in the EREF.
globally
shared page
TLB entry matches VA
=0?
=?
=?
AS (from MSR[IS] or MSR[DS])
PID0
EA Page Number bits
=?
TLB Entry
TS
TID EPN V
=?
=?
PID1
PID2