Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Register Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 2-11
MSR contents are read into a GPR using mfmsr. The contents of a GPR can be written to MSR
using mtmsr. The write MSR external enable instructions (wrtee and wrteei) can be used to set
or clear MSR[EE] without affecting other MSR bits.
Table 2-3 describes e500-specific MSR fields. Note that other registers in this chapter describe
only fields that are either e500-specific or that differ from the Book E definition.
Table 2-3. MSR Field Descriptions
Bits Name Description
32–36 — Reserved, should be cleared.
1
37 UCLE User-mode cache lock enable. (e500-specific). Used to restrict user-mode cache-line locking by the operating
system.
0 Any cache lock instruction executed in user-mode takes a cache-locking DSI exception and sets either
ESR[DLK] or ESR[ILK]. This allows the operating system to manage and track the locking/unlocking of cache
blocks by user-mode tasks.
1 Cache-locking instructions can be executed in user-mode and they do not take a DSI for cache-locking. (They
may still take a DSI for access violations, though.)
38 SPE SPE enable. (e500-specific).
0 If software attempts to execute an instruction that accesses the upper word of a GPR, the SPE APU
unavailable exception is taken.
1 Software can execute the following instructions:
On the e500v1, these instructions include the SPE instructions and both vector and scalar single-precision
floating-point instructions.
On the e500v2, these instructions include the SPE instructions, embedded double-precision, and
single-precision vector floating-point instructions. (That is, all instructions that access the upper half of the
64-bit GPRs.)
39–44 — Reserved, should be cleared.
1
45 WE Wait state enable. On the e500, this allows the core complex to signal a request for power management,
according to the states of HID0[DOZE], HID0[NAP], and HID0[SLEEP].
0 The processor is not in wait state and continues processing. On the e500, no power management request is
signaled to external logic.
1 The processor enters wait state by ceasing to execute instructions and entering low-power mode. Details of
how wait state is entered and exited and how the processor behaves in the wait state are implementation
dependent. On the e500, MSR[WE] gates the DOZE, NAP, and SLEEP outputs from the core complex; as a
result, these outputs negate to the external power management logic on entry to the interrupt and then return
to their previous state on return from the interrupt. WE is cleared on entry to any interrupt and restored to its
previous state upon return.
46 CE Critical enable. Book E defines this bit as an enable for the critical input, watchdog timer, and machine check
interrupts. On the e500, this bit does not affect machine check interrupts.
0 Critical input and watchdog timer interrupts are disabled.
1 Critical input and watchdog timer interrupts are enabled.
47 — Reserved, should be cleared.
48 EE External enable
0 External input, decrementer, fixed-interval timer, and performance monitor interrupts are disabled.
1 External input, decrementer, fixed-interval timer, and performance monitor interrupts are enabled.
49 PR User mode (problem state)
0 The processor is in supervisor mode, can execute any instruction, and can access any resource (for example,
GPRs, SPRs, and the MSR).
1 The processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged
resource.
PR also affects memory access control.