Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-11
have reported all exceptions they cause. Assume that valid TLB entries exist for the target memory
location when the sequence starts.
1. A program issues a load or store to a page.
2. The same program executes a tlbwe or tlbivax that invalidates the corresponding TLB
entry.
3. The load or store instruction finally executes, and gets a TLB miss exception.
The TLB miss exception is semantically incorrect. To prevent it, a context-synchronizing
instruction must be executed between steps 1 and 2.
3.2.3.3 Context Synchronization
An instruction or event is context synchronizing if it satisfies the requirements listed below.
Context-synchronizing operations include instructions isync, sc, rfi, rfci, and rfmci, and most
interrupts.
1. The operation is not initiated or, in the case of isync, does not complete until all instructions
already in execution have completed to a point at which they have reported all exceptions
they cause.
2. The instructions that precede the operation complete execution in the context (including
such parameters as privilege level, address space, and memory protection) in which they
were initiated.
3. If the operation directly causes an interrupt (for example, sc directly causes a system call
interrupt) or is an interrupt, the operation is not initiated until no interrupt-causing
exception exists having higher priority than the exception associated with the interrupt.
See
Section 5.11, “Exception Priorities.”
4. The instructions that follow the operation are fetched and executed in the context established
by the operation as required by the sequential execution model. (This requirement dictates
that any prefetched instructions be discarded and that any effects and side effects of
executing them speculatively may also be discarded, except as described in the “Cache and
MMU Background” chapter in the EREF.)
As described in Section 3.2.3.4, “Execution Synchronization,” a context-synchronizing operation
is necessarily execution synchronizing. Unlike msync and mbar, such operations do not affect the
order of memory accesses with respect to other mechanisms.
3.2.3.4 Execution Synchronization
An instruction is execution synchronizing if it satisfies items 1 and 2 of the definition of context
synchronization (see
Section 3.2.3.3, “Context Synchronization” ). msync is treated like isync
with respect to item 1 (that is, the conditions described in item 1 apply to completion of msync).