Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Guidelines for 32-Bit Book E
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor B-3
32-bit real addresses by supporting more than bits 32–53 of the real page number (RPN) field in
the TLB.
B.5 32-Bit Book E Software Guidelines
This section describes instruction selection and addressing of 32-bit software.
B.5.1 32-Bit Instruction Selection
Any Book E software that uses any of the instructions listed in Section B.1, “64-Bit–Specific Book
E Instructions ,” is considered 64-bit Book E software, and correct execution cannot be guaranteed
on 32-bit Book E implementations. Generally speaking, 32-bit software should avoid instructions
that depend on any particular setting of bits 0–31 of any 64-bit application-accessible system
register, including GPRs, for producing the correct 32-bit results. Context switching is not required
to preserve the upper 32 bits of application-accessible 64-bit system registers and insertion of
arbitrary settings of those upper 32 bits at arbitrary times during the execution of the 32-bit
application must not affect the final result.
B.5.2 32-Bit Addressing
Book E provides a complete set of data memory access instructions that perform a modulo 2
32
on
the computed effective address and then prepend 32 zeros to produce the full 64-bit address.
Book E also provides a complete set of branch instructions that perform a modulo 2
32
on the
computed branch target effective address and then prepend 32 zeros to produce the full 64-bit
branch target address. On a 32-bit Book E implementation, these instructions are executed as
defined, but without prepending the 32 zeros (only the low-order 32 bits of the address are
calculated). On a 64-bit implementation, executing these instructions as defined provides the
effect of restricting the application to lowest 32-bit address space.
However, there is one exception. Next sequential instruction address computations (not a taken
branch) are not defined for 32-bit Book E applications when the current instruction address is
0xFFFF_FFFC. On a 32-bit Book E implementation, the instruction address could simply wrap to
0x0000_0000, providing the same effect that is required in the PowerPC Architecture. However,
when the 32-bit Book E application is executed on a 64-bit Book E implementation, the next
sequential instruction address calculated will be 0x0000_0001_0000_0000 and not
0x0000_0000_0000_0000. To avoid this problem the 32-bit Book E application must either avoid
this situation by not allowing code to span this address boundary, or requiring a branch absolute
to address 0 be placed at address 0xFFFF_FFFC to emulate the wrap. Either of these approaches
allows the application to execute on 32-bit and 64-bit Book E implementations.