Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
13-8 Freescale Semiconductor
Core Complex Bus (CCB)
address/data transaction by the core complex to memory that requires read data to be returned to
the core complex. The read data, however, is not used or cached internally by the core complex.
The purpose for the bus transaction is to establish a locked line in the L2 cache and to make data
available from system memory for the L2 cache to capture.
Cache locking instructions targeted at an L2 cache may also hit to modified data in the L1 data
cache when they are executed. In this case, the core complex pushes the line from the L1 data
cache as a non-global burst write operation (similar to a regular L1 castout) and with the lock
attribute set and the write-through attribute negated, rather than performing a read bus operation
as described above. A front-side L2 cache may also recognize this transaction as a direction to
establish and capture the cache line and mark it as locked.
13.5.2 L2 Unlocking
When the core complex executes an instruction (dcblc, icblc) to unlock an L2 cache line, it
performs the associated bus operation as an address-only transaction with a tt[0:4] encoding of
CLEAN and with the lock attribute asserted. A front-side L2 cache may recognize this transaction
as a direction to unlock the specified address from its cache. This transaction is always performed
as non-global because it is specifically targeted at an L2 cache.
An L2 cache may also use other bus transactions to cause locks to be cleared, such as bus
transactions as a result of dcbf (identified on the bus as an address-only FLUSH) or as an L1 push
due to dcbf.
13.5.3 L1 Overlock
A program can attempt to over-lock the core complex’s L1 data cache by trying to establish a ninth
locked entry at a cache index that already has all of its 8 ways locked. In this case, the core complex
performs a reading transaction on the bus to initially bring in the ninth (newest) line and then
immediately pushes that line out to the bus as a nonglobal burst write with the lock attribute
asserted, rather than attempting to allocate that line in the L1 data cache. This write operation looks
identical on the bus as the one described in
Section 13.5.1, “L2 Locking ,” for hit-to-modified
cases.
13.6 Reservation Management
The core complex supports standard reservation management through the lwarx/stwcx.
instruction pair. This method of reservation management relies exclusively on bus snooping to
detect whether an atomic access to a reservation granule was successful.
For systems that require the implementation of atomic accesses without a requirement for bus
snooping, a following option is recommended. A system-defined atomic operation could be
implemented directly in the memory subsystem and keyed off of a unique bus transaction (such as