Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Core Complex Overview
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 1-31
1.12.1 Global Control Register
The PMGC0 register provides global control of the performance monitoring facility from
supervisor mode. From this register all counters may be frozen, unfrozen, or configured to freeze
on an enabled condition or event. Additionally, the performance monitoring facility may be
disabled or enabled from this register. The contents of PMGC0 are reflected to UPMGC0, which
may be read from user mode using the mfpmr instruction.
1.12.2 Performance Monitor Counter Registers
There are four counter registers (PCM0–PCM3) provided in the performance monitoring facility.
These 32-bit registers hold the current count for software-selectable events and can be
programmed to generate an exception on overflow. These registers may be written or read from
supervisor mode using the mtpmr and mfpmr instructions. The contents of these registers are
reflected to UPCM0–UPCM3, which can be read from user mode with mfpmr.
Performance monitor exceptions occur only if all of the following conditions are met:
• A counter is in the overflow state.
• The counter's overflow signaling is enabled.
• Overflow exception generation is enabled in PMGC0.
• MSR[EE] is set.
1.12.3 Local Control Registers
For each of the counter registers, there are two corresponding local control registers. These two
registers specify which of the 128 available events is to be counted, what specific action is to be
taken on overflow, and various options for freezing a counter value under given modes or
conditions.
• PMLCa0–PMLCa3 provide fields that allow freezing of the corresponding counter in user
mode, supervisor mode, or under software control. Additionally, the overflow condition
may be enabled or disabled from this register. The contents of these registers are reflected
to UPMLCa0–UPMLCa3, which can be read from user mode with mfpmr.
• PMLCb0–PMLCb3 provide count scaling for each counter register using configurable
threshold and multiplier values. The threshold is a 6-bit value and the multiplier is a 3-bit
encoded value, allowing eight multiplier values in the range of 1 to 128. Any counter may
be configured to increment only when an event occurs more than [threshold
×
multiplier]
times. The contents of these registers are reflected to UPMLCb0–UPMLCb3, which can be
read from user mode with mfpmr.