PowerPC e500 Core Family Reference Manual, Rev. 1
3-48
Freescale Semiconductor
Instruction Model
Programmers should be aware that the simple unit used is busy for one cycle executing the update
portion of the update instruction.
3.7
Memory Synchronization
The msync instruction provides a memory barrier throughout the memory hierarchy. It waits for
preceding data memory accesses to reach the point of coherency (that is, visible to the entire
memory hierarchy); then it is broadcast on the e500 core complex bus. Only after the address bus
tenure of the msync is successful (that is, without being ARTRYed) is msync completed. No
subsequent instructions in the stream are initiated until after msync completes. Note that msync
uses the same opcode as the sync instruction.
The msync instruction is described in
Section 3.3.1.6, “Memory Synchronization Instructions
.”
The e500 core complex implements two variations of the mbar instruction. The desired behavior
is selected with the MO field (bits 6–10) of mbar, as follows:
•
When MO = 0, mbar behaves as defined by the Book E architecture.
•
When MO = 1, the EIS defines mbar to function identically to the Classic PowerPC
architecture definition of eieio.
•
If MO is not 1, the e500 executes mbar as though MO = 0.
The e500 core complex implements lwarx and stwcx. as described in Book E. If the EA is not a
multiple of four for either instruction, an alignment interrupt is invoked. If either instruction tries
to access a page marked as write-through required, a DSI interrupt is invoked.
As specified in Book E, the e500 core complex requires that, for stwcx. to succeed, the EA of
stwcx. must be to the same reservation granule as the EA of a preceding lwarx. Reservation
granularity is implementation dependent. The e500 core complex makes reservations on behalf of
aligned 32-byte sections of the memory address space.
For the purposes of memory coherency, the reservation granule for lwarx and stwcx. is also a
cache block. A reservation-killing snoop to any address within a cache block that contains the
reservation causes the reservation to be invalidated.
The reservation is invalidated when an external interrupt is signaled.
3.8
EIS-Defined Instructions and APUs Implemented on
the e500
Instructions that are specific to the e500 core are implemented as auxiliary processing units
(APUs) and are described in the following sections.
Summary of Contents for PowerPC e500 Core
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