Freescale Semiconductor PowerPC e500 Core, Reference Manual

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L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-9
11.2.4 Cache Parity Error Injection
Cache parity error injection provides a way to test error recovery software by intentionally
injecting parity errors into the instruction and data caches, as follows:
• If L1CSR1[ICPI] is set, any instruction cache line fill has all of its parity bits inverted in
the instruction cache.
• If L1CSR0[CPI] is set, any data line fill has all of its parity bits inverted in the data cache.
Additionally, inverted parity bits are generated for any bytes stored into the data cache by
store instructions, dcbz, and dcba.
NOTE
L1 cache parity checking for the instruction cache must be enabled (L1CSR1[ICPE] = 1) when
L1CSR1[ICPI] is set. Similarly for the data cache, L1CSR0[CPE] must be set if L1CSR0[CPI] is
set. If the programmer attempts to set L1CSR0[CPI] (using mtspr) without setting L1CSR0[CPE],
then L1CSR0[CPI] will not be set. If the programmer attempts to set L1CSR1[ICPI] without
setting L1CSR1[ICPE], then L1CSR1[ICPI] will not be set.
As described above, if a cache parity error is detected, a machine check interrupt occurs. Sources
for cache parity errors are described in
Section 5.7.2, “Machine Check Interrupt .”
11.3 Cache Coherency Support
This section describes the L1 cache coherency models and coherency support.
11.3.1 Data Cache Coherency Model
The core complex data cache supports four-state cache coherency protocol for cache lines in the
data cache.The four-state protocol (also referred to as MESI protocol) includes the additional
shared state. This protocol supports efficient and frequent sharing of data between bus masters.